Hi TI,
Can the clock CLK of EMMC only be modified by an integer multiple of 100M / 200m? Can it be modified to some customized frequence, such as, like 198mhz? thanks
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Hi TI,
Can the clock CLK of EMMC only be modified by an integer multiple of 100M / 200m? Can it be modified to some customized frequence, such as, like 198mhz? thanks
Any feedback for this ticket? thanks
Hi Veitch,
What is your use-case? Are you going to use eMMC boot-mode?
regards
Suman
Hi Suman,
Yes, we are using the eMMC boot-mode, Currently we are setting 50Mhz for eMMC at uboot stage in the purpose of solving the sometimes boot fail issue , and re-configure it to 200Mhz in kernel.
But our hardware expert found the timing-sequence of eMMC communication is not perfect, especially at uboot stage, which may result in some unexpected issue, such as emmc write fail at uboot(50Mhz)
As for the kernel stage, our hardware expert found the doubling point of 200MHz in RE(Radiation emission) experiment exceeded the standard of 1.6GHz, so we'd like to to modify the EMMC clock to specific 198mhz in order to staggering the frequency doubling point of 1.6GHz.
In summary, we'd like to know if there's a way to set the eMMC frequence at uboot lower than 50Mhz, and set it to 198Mhz at kernel.
thanks
Veitch,
If you have the default configuration, the eMMC clock is derived from PLL0, which is typically set for 2000 MHz, and changing it to 198 MHz won't be straightforward. You will need to work with the Clock Tree Tool (https://www.ti.com/tool/CLOCKTREETOOL) based on your use case to decide which options are available, and if the frequency can even be supported on your setup.
Once you have a frequency identified, you can change the frequency in the corresponding board config file, under main_sdhci0() by defining max-frequency = <X frequency>;
It is concerning your system is failing boot up at 50 MHz. Does your team know the root-cause failures are happening?
Best Regards,
Shiou Mei