Other Parts Discussed in Thread: ADS4245
Hi,
We have DSP uPP_XD pins driven by ADS4245 port B and BOOT pins 2 and 3 are pulled up and the rest of the boot pins are pulled down to enable Flash Boot up configuration (BOOT[7:0] = b00001100). These are pulled up to 1.8 DRVDD. Can someone assist on why aren't we able to boot-up?
We make sure that 1.8 AVDD rail to ADS4245 is enabled by DSP and expect it to be disabled till DSP bootup. 1.8 DRVDD rail to ADS4245 is enabled all the time and the boot-pins are pulled up to this rail.
Should DSP pins be hi-Z on application of just the core voltage, so the BOOT pins are stable with respective pull-ups and pull-downs as 1.8AVDD rail is disabled till DSP programs from Flash?
Do we expect ADS4245 output pins to be hi-Z state if 1.8 AVDD rail is disabled?
What happens to outputs if we have 1.8 DRVDD pin enabled and 1.8AVDD is disabled?
Should DSP pins be hi-Z on application of just the core voltage till it loads the firmware from Flash?
Please assist.
