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TMS320C6657: PCIe Memory read/write process

Alson Richards
Prodigy 100 points

Part Number: TMS320C6657

I am working on a project that uses this DSP and the intention is to establish communications between the CPU and FPGA/Memory by means of the PCIe, with the onboard PCIE being the Root Complex and the FPGA containing an endpoint.

I have been studying PCIe documentation, mainly tms320c6657.pdf and sprugs6d.pdf but there is some information I cannot seem to find, ie how to initiate a read or write transaction to external PCIe device. My research into PCIe in general refers to TLP header/packets but I can't find that documented in any of the TI documentation I have in my possession. What am I missing? Does a memory write/read automatically get captured by the PCIe and processed that way or am I missing something? 

Thanks

  • 0
    Guru 13202 points

    Hello!

    Making simple read or write is fairly easy: just make read or write access to PCIe data memory window, see Table 6-63. Memory Map Summary in data sheet. In its simplest form, when no address translation is applied, any memory access to 0x60000000~0x6FFFFFFF window will be served by PCIe peripheral. One may use macro like CONTENTS_OF() to do that. Be ready to see poor write and extremely poor read performance. To get more one have to use DMA, which can serve multiple data words with each TLP. That also requires certain support on FPGA side.

    Hope this helps

  • 0 in reply to Victor Kazmirenko
    Prodigy 100 points

    Okay I see. Thanks for the reply. I suppose that the BAR registers will be configured based on the size of the actual memory.

    What do you mean when no address translation is applied? When would address translation be necessary? 

  • +1 in reply to Alson Richards
    Guru 13202 points

    Hi again,

    Basically, yes, BAR configuration might be related to memory size behind it. Multiple BARs allow to have multiple memory windows withing PCIe data space, they could be different memory mapped devices in your end point.

    May I suggest to skim through PCIe Use Cases for KeyStone Devices Application Report, it's rather dense and presents real life examples, particularly about address translation, but has more info than I could type here. 

  • 0
    TI__Expert 4314 points

    Hi Alson,

    In addition to Victor's rely, Please try with "PCIE_evmc6657_wSoCFile_C66BiosExampleProject" and "PCIE_evmc6657_wSoCLib_C66BiosExampleProject". in C6657 RTOS SDK.

    Thanks,

    Rajarajan U