DRA821U: Question of the configuration of MCU_SYSCLK0

He Fang

Part Number: DRA821U

Hi experts:

1， If MCU_PLL0_HSDIV0_CLKOUT frequency is 1GHz,and The default configure value of WKUP_PLLCTRL0 module is as follow. Is MCU_SYSCLK0 default frequency 1GHz/24 = 41.67MHz?

2, Could our users change the default MCU_SYSCLK0 frequency to speed up the CBASS and related modules. Which config value of PLLDIV2 is suitable？

Thanks.

Fang He

over 3 years ago

0 KB over 3 years ago

TI__Guru** 120721 points

Hi,

Regarding (1), the "k3conf dump clocks" command can be used at the command prompt, on the target, to show configured clock settings.

Regarding (2), team will follow up.

+1 Kevin Lavery over 3 years ago

TI__Mastermind 20030 points

Fang,

Section 5.4.5.6 PLL and PLL Controller Connection of the TRM shows that (MCU_)SYSCLK0 is controlled by PLLDIV0; in this case, you are incremented from 1 so it is PLLDIV1. (The value of 0x8000 enables the clock with a divider of 1)

SYSCLK0 runs at 500MHz

MCU_SYSCLK0 runs at 1000MHz

It is NOT recommended to increase the bus speed.

Kevin

0 Yu Kui over 3 years ago in reply to Kevin Lavery

Intellectual 695 points

Hi expert,

In section 5.4.5.6, PLL controller uses PLLDIV0.

why we choose the PLLDIV1? and PLLDIV2 value is 0x8017, what is the funtionality of PLLDIV2?

+1 Kevin Lavery over 3 years ago in reply to Yu Kui

TI__Mastermind 20030 points

PLLDIV2 drives a different SYSCLK output from the PLLCTRL which is not functionally used in the design.

Kevin

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DRA821U: Question of the configuration of MCU_SYSCLK0