Other Parts Discussed in Thread: SYSCONFIG
Our board had two ethernet ports, one with am65-cpsw-nuss , the other was from PRU, am65-cpsw-nuss works fine, but the PRU ethernet didn’t work. It can display eth1 when we type “ifconfig” in console , but the link led status were all wrong.
Our PRU ethernet connect a DP83822IRHBR (PHY chip) with MII interface,
My question is: how to customize this DP83822 to fit this PRU ethernet and make it work?
Its schematic diagram is as follow:
now its setting in DTS list as follow:
/* Dual Ethernet application node on PRU-ICSSG0 */
icssg0_eth: icssg0-eth {
compatible = "ti,am654-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg0_mii_pins_default>;
sram = <&msmc_ram>;
ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
mii-g-rt = <&icssg0_mii_g_rt>;
mii-rt = <&icssg0_mii_rt>;
iep = <&icssg0_iep0>, <&icssg0_iep1>;
interrupt-parent = <&icssg0_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_udmap 0xc100>, /* egress slice 0 */
<&main_udmap 0xc101>, /* egress slice 0 */
<&main_udmap 0xc102>, /* egress slice 0 */
<&main_udmap 0xc103>, /* egress slice 0 */
<&main_udmap 0xc104>, /* egress slice 1 */
<&main_udmap 0xc105>, /* egress slice 1 */
<&main_udmap 0xc106>, /* egress slice 1 */
<&main_udmap 0xc107>, /* egress slice 1 */
<&main_udmap 0x4100>, /* ingress slice 0 */
<&main_udmap 0x4101>, /* ingress slice 1 */
<&main_udmap 0x4102>, /* mgmnt rsp slice 0 */
<&main_udmap 0x4103>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
icssg0_emac0: ethernet-mii0 {
phy-handle = <&icssg0_phy0>;
phy-mode = "mii";
syscon-rgmii-delay = <&scm_conf 0x4100>;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
/*
icssg0_emac1: ethernet-mii1 {
phy-handle = <&icssg0_phy1>;
phy-mode = "rgmii-rxid";
syscon-rgmii-delay = <&scm_conf 0x4104>;
/* Filled in by bootloader
local-mac-address = [00 00 00 00 00 00];
};*/
};
……….
icssg0_mdio_pins_default: icssg0-mdio-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
>;
};
icssg0_mii_pins_default: icssg0-mii-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0284, PIN_INPUT_PULLDOWN, 1) /* (AC24) PRG0_PRU1_GPO16.pr0_mii_mt0_clk */
AM65X_IOPAD(0x0280, PIN_OUTPUT_PULLDOWN, 0) /* (AE27) PRG0_PRU1_GPO15.pr0_mii0_txen */
AM65X_IOPAD(0x027c, PIN_OUTPUT_PULLDOWN, 0) /* (AD24) PRG0_PRU1_GPO14.pr0_mii0_txd3 */
AM65X_IOPAD(0x0278, PIN_OUTPUT_PULLDOWN, 0) /* (AD25) PRG0_PRU1_GPO13.pr0_mii0_txd2 */
AM65X_IOPAD(0x0274, PIN_OUTPUT_PULLDOWN, 0) /* (AC25) PRG0_PRU1_GPO12.pr0_mii0_txd1 */
AM65X_IOPAD(0x0270, PIN_OUTPUT_PULLDOWN, 0) /* (AB24) PRG0_PRU1_GPO11.pr0_mii0_txd0 */
AM65X_IOPAD(0x0204, PIN_INPUT_PULLDOWN, 1) /* (Y24) PRG0_PRU0_GPO4.pr0_mii0_rxdv */
AM65X_IOPAD(0x020c, PIN_INPUT_PULLDOWN, 1) /* (Y25) PRG0_PRU0_GPO6.pr0_mii_mr0_clk */
AM65X_IOPAD(0x0200, PIN_INPUT_PULLDOWN, 1) /* (AA27) PRG0_PRU0_GPO3.pr0_mii0_rxd3 */
AM65X_IOPAD(0x01fc, PIN_INPUT_PULLDOWN, 1) /* (W24) PRG0_PRU0_GPO2.pr0_mii0_rxd2 */
AM65X_IOPAD(0x021c, PIN_INPUT_PULLDOWN, 1) /* (U25) PRG0_PRU0_GPO10.pr0_mii0_crs */
AM65X_IOPAD(0x0208, PIN_INPUT_PULLDOWN, 1) /* (V28) PRG0_PRU0_GPO5.pr0_mii0_rxer */
AM65X_IOPAD(0x01f8, PIN_INPUT_PULLDOWN, 1) /* (W25) PRG0_PRU0_GPO1.pr0_mii0_rxd1 */
AM65X_IOPAD(0x01f4, PIN_INPUT_PULLDOWN, 1) /* (V24) PRG0_PRU0_GPO0.pr0_mii0_rxd0 */
AM65X_IOPAD(0x0218, PIN_INPUT_PULLDOWN, 1) /* (V26) PRG0_PRU0_GPO9.pr0_mii0_col */
AM65X_IOPAD(0x0214, PIN_INPUT_PULLDOWN, 1) /* (V27) PRG0_PRU0_GPO8.pr0_mii0_rxlink */
>;
};
icssg0_iep0_pins_default: icssg0-iep0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
>;
};
………
&icssg0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&icssg0_mdio_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
icssg0_phy0: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
/*
icssg0_phy1: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};*/
};
&icssg0_iep0 {
pinctrl-names = "default";
pinctrl-0 = <&icssg0_iep0_pins_default>;
};
&icssg0_eth {
compatible = "ti,am654-icssg-prueth-sr1";
ti,prus = <&pru0_0>, <&rtu0_0>, <&pru0_1>, <&rtu0_1>;
firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf",
"ti-pruss/am65x-rtu0-prueth-fw.elf",
"ti-pruss/am65x-pru1-prueth-fw.elf",
"ti-pruss/am65x-rtu1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>, /* MII mode */
<2>;
};
&icssg0_iep0 {
interrupt-parent = <&icssg0_intc>;
interrupts = <7 7 8>;
interrupt-names = "iep_cap_cmp";
};
&icssg0_iep1 {
interrupt-parent = <&icssg0_intc>;
interrupts = <56 8 9>;
interrupt-names = "iep_cap_cmp";
};
&tx_pru0_0 {
status = "enabled";
};
