Version
NDK:ndk_3_80_00_19
NS:ns_2_80_00_17
PDK:pdk_jacinto_07_03_00_29
Background: CPSW9G only opens Mac Port7, Use RMII
Hi :
1) Is there duplication in the chip manual? [SPRUIL1B.pdf]
12.2.2.4.6.1.9.6 VLAN/Unicast Address Table Entry (Bit 40 == 0)
12.2.2.4.6.1.9.4 VLAN Unicast Address Table Entry (Bit 40 == 0)
2) according to the logic in the gel code , when bit[60,61] ( i.e. ENTRY_TYPE) == 2h, it is determined by the relevant bits of bit[62,64].
But In the chip manual, the corresponding bits [62,64] are reserved (except Ipv6).
Based on the above situation, what is the basis of distinguishing Address Table Entry (when ENTRY_TYPE == 2h)?
3) In cpsw_ale_print_table. gel
(sdk/rtos/pdk_jacinto_07_03_00_29/packages/ti/drv/enet/tools/debug_gels), as shown below,
[
vlanEntryType = ((word1 > > 30) & 0x3);
vlanEntryType |= ((word2 > > 0) & 0x1);
]
So , only bit0 and bit1 can be 1 , and VlanEntryType ==0x4 and vlanEntryType==0x6 are not possible. Is there a problem with the assignment of vlanEntryType?
Hope you can spare time to help answer, thank you very much !
Best wishes !