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TMS320C6655: SRIO connection

Sung-IL
Mastermind 29980 points
Part Number: TMS320C6655

Dear Champs,

My customer would like to check their boot-up order if there is no timing issue to establish SRIO connection between DSP and FPGA, and their system configuration is as below.

In this case, FPGA which is SRIO slave device is boot-up after DSP which is SRIO host boot-up. e.g. DSP -> FPGA.

Could you please check if there is any SRIO connection issue in this case?

Thanks and Best Regards,

SI.

  • 0
    TI__Mastermind 25535 points

    SI,

    I am not an expert in SRIO.

    Just came across few info on https://www.ti.com/lit/an/sprac59a/sprac59a.pdf

    If this information does not suffice for the customer, please revert to me.....

    --- Extract from this doc -----

    Which version of FPGA firmware requires IBL for PCIe boot mode?

    Refer to Section 1.3. For FPGA v2, the program counter (PC) of the DSP will be inside LL2 and is booted from RBL to IBL (loaded from I 2C address 0x51 into LL2) and stay inside LL2 forever and will not jump back to RBL (0x20b0xxxx). For FPGA v3, it boot directly from RBL, no IBL is used. NOTE: This is applicable for the C6657 EVM only. All of the FPGA versions of the C6678 EVM require IBL for PCIe boot mode. Refer to the EVM page for more information.

    Regards

    Shankari G

  • 0 in reply to Shankari G
    TI__Mastermind 29980 points

    Hi Shankari,

    As you may understand, I'm asking about SRIO, not PCIe.

    I can not understand what is related with SRIO in the captured information, and I think it is only mentioning PCIe. Could you please provide more details on this information how it will be explained the boot sequence of devices connected through SRIO?

    e.g. When FPGA was connected to C6655 DSP through SRIO and FPGA is SRIO slave, it is OK to boot-up DSP first and then FPGA. And also I would like to check if there is any time limitation to detect slave from host.

    Thanks and Best Regards,

    SI.

  • 0 in reply to Sung-IL
    TI__Mastermind 25535 points

    SI,

    When I looked into your diagram and your explanation says, DSP will boot first.( Is this a PCIE boot ? ) and then FPGA  boots ( in SRIO boot mode ),  So, I understood the query as "PCIE boot" and hence provided info on PCIE.

    For SRIO boot, please have a look at this thread,

    DSP 6670 SRIO Boot loader example - Processors forum - Processors - TI E2E support forums 

    where in, it mentioned about the Host EVM ( running the SRIO-boot-load-example-code via JTAG through CCS) and the Boot EVM ( which is booted using SRIO boot mode ) 

    --

    For your design, are you planning to have the "FPGA" in place of "BOOT EVM?"  and the HOST EVM will remain as DSP-C6655 ?? 

    Let me forward your query to internal team.

    Regards

    Shankari G

  • 0 in reply to Shankari G
    TI__Mastermind 25535 points

    SI,

    As of now, no SRIO experts, available, to validate your customized requirement on the BOOT flow ( With PCIE and SRIO ).

    Thanks for understanding!.

    Regards

    Shankari G