Hi All,
On the OMAP_L138 EVM, I want to use McASP0 in receive mode (using 2-slot TDM I2S mode) . Master Clock (AHCLKR) is generated externally while Bit Clock (ACLKR) and frame sync (AFSR) are generated internally.
In the McASPSampleMaster project under pspdrivers_01_30_01
1) There is this 'mcaspParams' in mcaspSampleMaster_main.c. It provides the access to set the McASP Clocks, Data pin direction and Data Format. And there is 'Mcasp_HwSetupData', which is used for the Mcasp_ChanParams setting, in mcaspSampleMaster_io.c. 'Mcasp_HwSetupData' also have McASP clocks and Data Format setting.
Are they the same thing and only need to be set once? If no, then which is the once that I need to use (in order to configure McASP to a 2 channel I2S)?
2) If the answer to my 1) question is yes. I have tried to set the 'Mcasp_HwSetupData' to the following value, but the register are not what I set when I debug it. Did I do something wrong?
3) To save more time, is there a document about how the BIOS PSP works? I could see the source code, but don't know when and where it is called.
The tools that I am using:
CCS V4.2.1.00004
BIOS 5_41_10_36
EDMA edma3_lld_01_10_00_01
pspdrivers_01_30_01
Any suggestion will be appreciated.
Regards,
Sarah
Mcasp_HwSetupData mcaspRcvSetup =
{
/* .rmask = */ 0xFFFFFFFF, /* all Data bits are used */
/* .rfmt = */ 0x00018070, /* Receive Bit Stream Format Register
* (31-18 Bits) Reserved
* (17-16) RDATDLY - 1 bit delay (for I2S format),
* (15) RRCRS - MSB first,
* (14-13) RPAD - No pad value for extra bits in slot
* (12-8) RPBIT - ignored (only used when RPAD not 0)
* (7-4) RSSZ - 16 bits slot size
* (3) RBUSEL - Reads from XRBUF on DMA port.
* (2-0) RROT - No rotation */
/* .afsrctl = */ 0x00000113, /* Receive Frame Sync Control Register
* (31-16) Reserved
* (15-7) RMOD - I2S mode (2-slot TDM)
* (6-5) Reserved
* (4) FRWID - Single word (width of receive Frame Sync
* (3-2) Reserved
* (1) FSRM - Internally-generated receive frame sync
* (0) FSRP - A failling edge (for I2S) indicates beginning of frame */
/* .rtdm = */ 0x00000003, /* Receive TDM Time Slot Register
* only 2 slots active (for I2S) */
/* .rintctl = */ 0x00000003, /* Receiver Interrupt Control Register
* underrun and sync error active (For now, might need change in future) */
/* .rstat = */ 0x000001FF, /* Receiver Status Register
* reset any existing status bits */
/* .revtctl = */ 0x00000000, /* Receiver DMA Event Control Register
* DMA mode */
{
/* .aclkrctl = */ 0x0000003F, /* Receive Clock Control Register,
* (31-8) Reserved
* (7) CLKRP - Falling edge. (don't know what it means)
* (6) Reserved
* (5) CLKRM - internal
* (4-0) CLKRDIV - divide by 32 */
/* .ahclkrctl = */ 0x0000000F, /* Receive High-Frequency Clock Control Register
* external, divide-by-16 */
/* .rclkchk = */ 0x00000000 /* Receive Clock Check Control Register */
}
};