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McASP set up

Other Parts Discussed in Thread: OMAPL138

Hi All,

On the OMAP_L138 EVM, I want to use McASP0 in receive mode (using 2-slot TDM I2S mode) . Master Clock (AHCLKR) is generated externally while Bit Clock (ACLKR) and frame sync (AFSR) are generated internally.

In the McASPSampleMaster project under pspdrivers_01_30_01

1) There is this 'mcaspParams' in mcaspSampleMaster_main.c.   It provides the access to set the McASP Clocks, Data pin   direction and Data Format.   And there is 'Mcasp_HwSetupData', which is used for the Mcasp_ChanParams setting, in mcaspSampleMaster_io.c. 'Mcasp_HwSetupData' also have McASP clocks and Data Format setting.  

Are they the same thing and only need to be set once? If no, then which is the once that I need to use (in order to configure McASP to a 2 channel I2S)?

2) If the answer to my 1) question is yes.  I have tried to set the 'Mcasp_HwSetupData' to the following value, but the register are not what I set when I debug it.  Did I do something wrong?

3) To save more time, is there a document about how the BIOS PSP works? I could see the source code, but don't know when and where it is called.

The tools that I am using:

CCS V4.2.1.00004

BIOS 5_41_10_36

EDMA edma3_lld_01_10_00_01

pspdrivers_01_30_01

 

Any suggestion will be appreciated.

Regards,

Sarah

Mcasp_HwSetupData mcaspRcvSetup =
{
    /* .rmask    = */ 0xFFFFFFFF,  /* all Data bits are used              */
    /* .rfmt     = */ 0x00018070,  /* Receive Bit Stream Format Register
                                     * (31-18 Bits) Reserved
                                     * (17-16) RDATDLY - 1 bit delay (for I2S format),
                                     * (15)    RRCRS   - MSB first,
                                     * (14-13) RPAD    - No pad value for extra bits in slot
                                     * (12-8)  RPBIT   - ignored (only used when RPAD not 0)                                    
                                     * (7-4)   RSSZ    - 16 bits slot size
                                     * (3)     RBUSEL  - Reads from XRBUF on DMA port.
                                     * (2-0)   RROT    - No rotation */
    /* .afsrctl  = */ 0x00000113,  /* Receive Frame Sync Control Register
                                     * (31-16) Reserved
                                     * (15-7)  RMOD    - I2S mode (2-slot TDM)
                                     * (6-5)   Reserved
                                     * (4)     FRWID      - Single word (width of receive Frame Sync
                                     * (3-2)   Reserved
                                     * (1)     FSRM    - Internally-generated receive frame sync
                                     * (0)     FSRP    - A failling edge (for I2S) indicates beginning of frame  */
    /* .rtdm     = */ 0x00000003,  /* Receive TDM Time Slot Register
                                     * only 2 slots active (for I2S)       */
    /* .rintctl  = */ 0x00000003,  /* Receiver Interrupt Control Register
                                     * underrun and sync error active (For now, might need change in future)      */
    /* .rstat    = */ 0x000001FF,  /* Receiver Status Register 
                                     * reset any existing status bits      */
    /* .revtctl  = */ 0x00000000,  /* Receiver DMA Event Control Register
                                     * DMA mode                            */
    {
         /* .aclkrctl  = */ 0x0000003F,  /* Receive Clock Control Register,
                                            * (31-8) Reserved
                                            * (7)    CLKRP    - Falling edge. (don't know what it means)
                                            * (6)    Reserved
                                            * (5)    CLKRM    - internal
                                            * (4-0)  CLKRDIV    - divide by 32 */
         /* .ahclkrctl = */ 0x0000000F,  /* Receive High-Frequency Clock Control Register
                                            * external, divide-by-16                     */
         /* .rclkchk   = */ 0x00000000   /* Receive Clock Check Control Register      */
                                           
    }
};

  • Hi Sarah,

    Sarah Zhang said:

    1) There is this 'mcaspParams' in mcaspSampleMaster_main.c.   It provides the access to set the McASP Clocks, Data pin   direction and Data Format.   And there is 'Mcasp_HwSetupData', which is used for the Mcasp_ChanParams setting, in mcaspSampleMaster_io.c. 'Mcasp_HwSetupData' also have McASP clocks and Data Format setting.  

    Are they the same thing and only need to be set once? If no, then which is the once that I need to use (in order to configure McASP to a 2 channel I2S)?

    The "mcaspParams" in mcaspSampleMaster_main.c is used while device creation (which uses the default values, refer Mcasp_PARAMS in Mcasp.c file) and the "Mcasp_HwSetupData" is being used while creating the channel (user can configure the Mcasp according to the requirement). Always, the device is created first and then the channel.

    Before answering to other query, I would like to ask some of the questions:

    1. Are you using the sample application and the driver provided in the 1.30.01?

    2. If you are using the sample application from the BIOS PSP 1.30.01, then did you modify the "mcaspSampleMaster_io.c"? It looks like there is some modifications, like you are configuring the McASP to receive the data? Am i right?

    3. If you are using the McASP to receive the data, then are you passing SIO_INPUT while creating the stream?   

    4. Are you using OMAPL138 EVM or the custom board?

    Thanks and Regards,

    Sandeep K

  • Hi Sandeep,

    Thank you for your reply.

    To your question:

    Sandeep Krishnaswamy said:

    1. Are you using the sample application and the driver provided in the 1.30.01?

    Yes, I started with the sample application provided in the pspdrivers_01_30_01.

    Sandeep Krishnaswamy said:

    2. If you are using the sample application from the BIOS PSP 1.30.01, then did you modify the "mcaspSampleMaster_io.c"? It looks like there is some modifications, like you are configuring the McASP to receive the data? Am i right?

    Yes, I modified the sample in order to set the McASP0 in receive mode(using 2-slot TDM I2S mode). For DSP, Master Clock (AHCLKR) is genetated externally while Bit Clock and frame Sync generated internally. And the final target is receive Data from ADC (AIC3106).

    Sandeep Krishnaswamy said:

    3. If you are using the McASP to receive the data, then are you passing SIO_INPUT while creating the stream?

    Yes, the following is what i did together with the Mcasp_HwSetupData (mcaspRcvSetup shown in my initial post).

    sioAttrs = SIO_ATTRS;

    sioAttrs.nbufs = numOfBufs;

    sioAttrs.align = BUFALIGN;

    sioAttrs.model = SIO_ISSUERECLAIM;

    sioAttrs.timeout = 10000; //Added due to SIO_reclaim() hang sometime.

    /* open the I/O streams for input only */

    inStream = SIO_create("/dioMcaspIN", SIO_INPUT, BUFLEN, &sioAttrs);

     

    Sandeep Krishnaswamy said:

    4. Are you using OMAPL138 EVM or the custom board?

    I am using OMAPL138 EVM at the moment. But will move to custom board eventually.

     

    Based on your answer  

    Sandeep Krishnaswamy said:

    The "mcaspParams" in mcaspSampleMaster_main.c is used while device creation (which uses the default values, refer Mcasp_PARAMS in Mcasp.c file) and the "Mcasp_HwSetupData" is being used while creating the channel (user can configure the Mcasp according to the requirement). Always, the device is created first and then the channel. 

     

    So Mcasp_PARAMS and Mcasp_HwSetupData are two different things. The thing is they both have access to set the receive clocks and data format. Then If I want to set the McASP0 in receive mode(using 2-slot TDM I2S mode) with Master Clock (AHCLKR) genetated externally while Bit Clock and frame Sync generated internally.

    1.which of the following is the right thing to do? I can't image I need both.

    1) in mcaspSamplemaster_main.c

    mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk = 0x00000060;

    mcaspParams.mcaspHwSetup.rx.clk.clkSetupClk = 0x0000003F;

    mcaspParams.mcaspHwSetup.rx.clk.clkSetupHiClk = 0x0000000F;

    mcaspParams.mcaspHwSetup.rx.frSyncCtl = 0x00000113;

     

    2) in mcaspSamplemaster_io.c(Using this, all the register value during debugging are not what I set in below)

    Mcasp_HwSetupData mcaspRcvSetup =

    {

    /* .rmask = */ 0xFFFFFFFF, /* all Data bits are used */

     

    /* .rfmt = */ 0x00018070,

    /* Receive Bit Stream Format Register

    *

    /* .afsrctl = */ 0x00000113,

    /* Receive Frame Sync Control Register

    /* .rtdm = */ 0x00000003,

    /* Receive TDM Time Slot Register - only 2 slots active (for I2S) */

    /* .rintctl = */ 0x00000003, /* Receiver Interrupt Control Register

    */

    /* .rstat = */ 0x000001FF,

    /* Receiver Status Register */

    /* .revtctl = */ 0x00000000,

    /* Receiver DMA Event Control Register -  DMA mode */

    {

    /* .aclkrctl = */ 0x0000003F, /* Receive Clock Control Register *

     (31-8) Reserved

    * (7) CLKRP - Falling edge. (don't know what it means)

    * (6) Reserved

    * (5) CLKRM - internal

    * (4-0) CLKRDIV - divide by 32 */

    /* .ahclkrctl = */ 0x0000000F,

    /* Receive High-Frequency Clock Control Register

    * external, divide-by-16 */

    /* .rclkchk = */ 0x00000000

    /* Receive Clock Check Control Register */

    }

    };

    2. The first  1) above does set the register value as I set, which 2) does NOT. However, neither of them could generate the right bit clock (should be master divided by 32), which is always the same with master clock. And SIO_reclaim() always failed with error code 9. Did I do something wrong or is there something I missed?

     

    I have tried too many things and the right direction will help me a lot.

    Thanks again,

    Sarah

  • Sarah,

    Basically to set the ACLKRCTL.CLKRDIV bit , the ACLKXCTL.SYNC bit should be made '1'. Otherwise the configuration of ACLKRCTL does not get reflected.

    So my advice is to put a break point at Mcasp_localConfigRcvSection() in the file Mcbsp.c and then modify the ACLKXCTL.SYNC bit and then observe the ACLKRCTL values are modified as per request or not.

    If above cannot be done, then using the mcaspParams.mcaspHwSetup.tx.clk.clkSetupClk enable the bit 6 (ACLKXCTL.SYNC) and then observe the ACLKRCTL values are modified as per request or not.

    let me know the result.

    Thanks and Regards,

    Sandeep K