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TDA4VM: about enet read mdio link reg fail

jie nic
Prodigy 151 points
Part Number: TDA4VM

Hi:

I use sdk8.1,in ti-processor-sdk-rtos-j721e-evm-08_01_00_11/pdk_jacinto_08_01_00_33,

we board use 88q2112 phy for cpsw_9G,

Manually set 100BASE-T1, read the phy state is linked, and then read the mdio linked register on the TDA4 side is always link down, what's going on?

pdk_jacinto_08_01_00_33\packages\ti\csl\src\ip\mdio\V5\priv\csl_mdio.c
CSL_MDIO_isPhyAlive
        CSL_FEXTR (hMdioRegs->LINK_REG, phyAddr, phyAddr);

88q2112 phy reg read  status linked,but read soc mdio linked reg is 0:

CSL_MDIO_isPhyAlive return 0

 

Thanks,

Regards,

Jie

  • 0
    Prodigy 151 points

    Hi,

    Additional instructions: read 88q2112 phy reg status is linke up，but read mdio link reg is link down in enet drv CSL_MDIO_isPhyAlive ，

    What's the matter with the above question?

  • 0 in reply to jie nic
    TI__Mastermind 23125 points

    Jie, 

    can you confirm how do you read phy register, as you mentioned:

     "read 88q2112 phy reg status is linke up", are you using the mido tool in linux command line, or you are reading the PHY directly?

    if former, you may need to print out params passed in to:

       CSL_FEXTR (hMdioRegs->LINK_REG, phyAddr, phyAddr);

    I am not sure if the PHY has extended registers that the direct read tool interpreted differently than CSL function. 

    Jian

  • 0 in reply to jian35385
    Prodigy 151 points

    Hi Jian：

    I use EnetPhy_readC45Reg function read 88q2112 phy reg in enet drv:

    pdk_jacinto_08_01_00_33\packages\ti\drv\enet\src\phy\enetphy.c

    EnetPhy_linkWaitState -> EnetPhy_readC45Reg(hPhy, 0x07, 0x0201, &status);

    the status is link up

    then will enter  EnetPhy_linkedState：

    EnetPhy_linkedState ---> EnetPhy_isPhyLinked(hPhy);

    EnetPhy_isPhyLinked --> CSL_FEXTR (hMdioRegs->LINK_REG, phyAddr, phyAddr);

    it return link 0

    i use main mdio to connect 88q2112 phy

    regards

    Jie

  • 0 in reply to jian35385
    Prodigy 151 points

    Hi Jian:

    Additional instructions: 

    EnetPhy_isPhyLinked --> CSL_FEXTR (hMdioRegs->LINK_REG, phyAddr, phyAddr);

    hMdioRegs addr is 0x0C000F00

  • 0 in reply to jian35385
    Prodigy 70 points

    Hi Jian,

     Please help to check our issuses. Thank you.

  • 0 in reply to Cansheng Lin
    TI__Mastermind 23125 points

    Jie/Cansheng, 

    can you confirm what is the register setting for:

       CPSW0_NUSS_MDIO  at address 0x0C000F3C

    regards

    Jian

  • 0 in reply to jian35385
    Prodigy 151 points

    Hi Jian：

    We have configured CPSW0_NUSS_MDIO address at 0x0C000F3C

    regards

    Jie

  • 0 in reply to jian35385
    Prodigy 151 points

    Hi Jian：

    I re-check and need to correct what I said before

    We have configured CPSW0_NUSS_MDIO address at 0x0C000F00h

    in tda4 datasheet the CPSW0_NUSS_MDIO  address at 0x0C000F00h, not set address 0x0C000F3C

    regards

    Jie

  • 0 in reply to jian35385
    Prodigy 151 points

    Hi Jian:

    the CPSW_MDIO_LINK_REG address at 0x0C000F3C

    CPSW_MDIO_CLAUS45_REG address at 0x0C000F3C

    we use mdio clause45 read phy,and set CPSW_MDIO_CLAUS45_REG enable clause45

    Is the reading of mdio link different after setting c45 to access phy?

    mdio c45 reading the link register of 88q2112 phy is link up,

    so why is reading CPSW_MDIO_LINK_REG always 0 in EnetPhy_linkWaitState?

    regards

    Jie