It is my understanding that, in general, voltage should not be sourced into an I/O line (or at least current should be significantly limited) until the I/O bank power rail is powered up. Otherwise, the ESD structure clamping diodes can shunt the voltage to the power rail and prematurely raise its voltage.
I have a scenario where we have a SOM module with the DRA821U and PMIC Power solution (PCIe master) that is then inserted into a carrier board (PCIe slave) with its own separate power sequencing requirements (FPGA) that will start asynchronous to the DRA821U power sequencing. In this scenario, it is going to be extremely difficult to sequence the SERDES power rails on the DRA821U at the same time as the SERDES power rails on the FPGA. It is also not possible to add any significant series resistant on these high speed lines to limit clamping current.
I'm wondering if there is a sequencing concern with the SERDES I/O and power rail sequencing on the respective devices coming up asynchronously. If for example, the SERDES lines do not enable their outputs, or if the outputs are driven low, until the software initializes the PCIe and SERDES peripherals, then I do not expect any issue with voltage being present that would clamp to the power rails through the ESD structures.
The SOM and carrier board share a common ground reference.
Please advise.
Thanks,
Stuart
