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McBSP PSP driver does not set DX Enable mode

Jeremiah Ferguson
Intellectual 385 points

I am using PSP drivers 1.30.01 on a custom C6748 board. The device is configured as a slave on the McBSP bus that has been configured in TDM mode. In my configuration, I using the Mcbsp_DxENA_ON flag. However, if I pause execution and look at the actual register settings in a debug window, this value is set to 0 (off). Is this a bug in the PSP driver?

 

 

 

 

 

 

 

Mcbsp_DataConfig Mcbsp0TXChanConfig =

{

Mcbsp_Phase_SINGLE,

Mcbsp_WordLength_32,

Mcbsp_WordLength_32,

 

care */Dont/*

NUM_OF_CHANNELS,

NUM_OF_CHANNELS,

 

care */Dont/*

Mcbsp_FrmSync_DETECT,

Mcbsp_DataDelay_1_BIT,

Mcbsp_Compand_OFF_MSB_FIRST,

Mcbsp_BitReversal_DISABLE,

Mcbsp_IntMode_ON_SYNCERR,

 

_LZF, RxJUST_RxJust_Mcbsp

/* Dont care for TX */

Mcbsp_DxEna_ON

};

Mcbsp_DataConfig Mcbsp0RXChanConfig =

{

Mcbsp_Phase_SINGLE,

Mcbsp_WordLength_32,

Mcbsp_WordLength_32,

 

care */Dont/*

NUM_OF_CHANNELS,

NUM_OF_CHANNELS,

 

care */Dont/*

Mcbsp_FrmSync_DETECT,

Mcbsp_DataDelay_1_BIT,

Mcbsp_Compand_OFF_MSB_FIRST,

Mcbsp_BitReversal_DISABLE,

Mcbsp_IntMode_ON_SYNCERR,

 

_LZF, RxJUST_RxJust_Mcbsp

/* Dont care for TX */

Mcbsp_DxEna_ON

};

 

 

Mcbsp_ClkSetup Mcbsp0TXClkConfig =

{

Mcbsp_FsClkMode_EXTERNAL,

96000,

 

/* 96KHz ????? */

Mcbsp_TxRxClkMode_EXTERNAL,

Mcbsp_FsPol_ACTIVE_HIGH,

Mcbsp_ClkPol_RISING_EDGE

};

Mcbsp_ClkSetup Mcbsp0RXClkConfig =

{

Mcbsp_FsClkMode_EXTERNAL,

96000,

 

/* 96KHz ????? */

Mcbsp_TxRxClkMode_EXTERNAL,

Mcbsp_FsPol_ACTIVE_HIGH,

Mcbsp_ClkPol_RISING_EDGE

};

Mcbsp_McrSetup Mcbsp0TXMultiChanCtrl =

{

Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED,

Mcbsp_PartitionMode_CHAN_0_15,

Mcbsp_PartitionMode_CHAN_0_15,

Mcbsp_PartitionMode_8

};

Mcbsp_McrSetup Mcbsp0RXMultiChanCtrl =

{

Mcbsp_McmMode_ALL_CHAN_DISABLED_UNMASKED,

Mcbsp_PartitionMode_CHAN_0_15,

Mcbsp_PartitionMode_CHAN_0_15,

Mcbsp_PartitionMode_8

};

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mcbsp_ChanParams Mcbsp0TXChanparam =

{

 

_32, WordLength_Mcbsp

/* wordlength configured */

 

 

NULL,

/* loop job buffer internal */

0,

 

length */loopjob/* user

 

 

NULL,

/* global error callback */

 

 

NULL,

Handle */edma/*

1,

 

/* EDMA event queue */

8,

 

number */hwi/*

Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED,

FALSE,

 

/* FIFO mode enabled */

&Mcbsp0TXChanConfig,

 

/* channel configuration */

&Mcbsp0TXClkConfig,

 

/* clock configuration */

&Mcbsp0TXMultiChanCtrl,

 

/* multi channel control */

0x00007FFF,

 

//Channel enable mask for X/RCERE0

0x00000000,

 

//Channel enable mask for X/RCERE1 40-47

0x00000000,

 

//Channel enable mask for X/RCERE2

0x00000000

 

//Channel enable mask for X/RCERE3

};

Mcbsp_ChanParams Mcbsp0RXChanparam =

{

 

_32, WordLength_Mcbsp

/* wordlength configured */

 

 

NULL,

/* loop job buffer internal */

0,

 

length */loopjob/* user

 

 

NULL,

/* global error callback */

 

 

NULL,

Handle */edma/*

1,

 

/* EDMA event queue */

8,

 

number */hwi/*

Mcbsp_BufferFormat_MULTISLOT_INTERLEAVED,

FALSE,

 

/* FIFO mode enabled */

&Mcbsp0RXChanConfig,

 

/* channel configuration */

&Mcbsp0RXClkConfig,

 

/* clock configuration */

&Mcbsp0RXMultiChanCtrl,

 

/* multi channel control */

0x00007FFF,

 

//Channel enable mask for X/RCERE0

0x00000000,

 

//Channel enable mask for X/RCERE1 40-47

0x00000000,

 

//Channel enable mask for X/RCERE2

0x00000000

 

//Channel enable mask for X/RCERE3

};

 

  • 0
    TI__Expert 5500 points

    Hi Jeremiah,

     

    It looks like the ‘DxEna’ option provided in the application is not being used by the McBSP driver to update the DxENA bit of the SPCR register. Since the default value itself is ‘Mcbsp_DxEna_OFF’ the present application works fine without any issues.

     

    Well, If you need the DX Enabler ON, and to be affected in the McBSP registers, It would be better if you add the following piece of code in the driver file(Mcbsp.c) in the function Mcbsp_localConfigureXmtChannel(…) and then build the driver.

     

        instHandle->hwInfo.regs->SPCR |= (params->chanConfig-> dxState << CSL_MCBSP_SPCR_DXENA_SHIFT);

     

    Please try this, and let us know the results. Then we will decide what is to be done next.

     

    Thanks & regards,

    Raghavendra

  • 0 in reply to Raghavendra Maddikery
    Intellectual 385 points

    I have not yet had a chance to implement this, but I am sure it will work.

    For my needs, this is an absolute defect. I am using the McBSP in a TDM configuration with 14 devices on the same bus potentially pumping out a lot of data. In our configuration, I can not have a dead channel in between every device on the bus. I will have a chance to recompile and test this change early next week.

  • 0 in reply to Jeremiah Ferguson
    Intellectual 385 points

    The code with a slight change works.

    I ended up adding the following code to the top of the function.

    /* configure the DX enabler */

    instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_DXENA_MASK);

    instHandle->hwInfo.regs->SPCR |=

        (params->chanConfig->dxState << CSL_MCBSP_SPCR_DXENA_SHIFT);

  • 0 in reply to Jeremiah Ferguson
    TI__Expert 5500 points

    Hi Jeremiah,

     

    Well, thats good its working fine. But if you implement as suggested in the above post, it is equivalent to hardcoding DX enabler ("ON"). I request you to check with this piece of code and test it..

    instHandle->hwInfo.regs->SPCR |= (params->chanConfig-> dxState << CSL_MCBSP_SPCR_DXENA_SHIFT);

    This is because here, the DX Enabler bit is set depending on the "dxState" value which is sent from the application. So depending on this, the DX Enbler is ON or OFF.

    Please let me know the results, so that i can raise an IR which can be fixed in the future release.

    Thanks & regards,

    Raghavendra

  • 0 in reply to Raghavendra Maddikery
    Intellectual 385 points

    Please look carefully at the code I posted. The first step is to clear the bit so that it is in the off state. Next, I use you EXACT same line of code to set the bit as configured by the dxState.

    If your suggestion is used, on a soft reboot if the DXENA bit is already high and you want to set it low, just OR-ing the low state does nothing, the bit stays high. To properly work, as is done elsewhere in the function, the bit needs to be cleard first before OR-ing in the configured state.

  • 0 in reply to Jeremiah Ferguson
    TI__Expert 5500 points

    Hi Jeremiah,

     

    Thanks for an update on this!. I somehow missed noticing "dxState". Well, we shall go ahead and raise an IR on this and fix this issue by implementing..

    instHandle->hwInfo.regs->SPCR &= (~CSL_MCBSP_SPCR_DXENA_MASK);

    instHandle->hwInfo.regs->SPCR |= (params->chanConfig->dxState << CSL_MCBSP_SPCR_DXENA_SHIFT);

     

    Thanks & regards,

    Raghavendra

  • 0 in reply to Raghavendra Maddikery
    TI__Expert 5500 points

    Hi Jeremiah,

     

    An IR (SDOCM00081081) has been raised to keep in track of this issue. This will be fixed in the future release.

     

    Thanks & regards,

    Raghavendra