AM5708：AM5708：PCIe x2 Gen2 Link faile

Yu, 

Sorry that previously thread was locked. I saw you and Brad has some discussions that has not been concluded. so reassigning the this thread to his attention. 

On the external clock configuration, I think you will need to be the external clock setup before the PCIe reset. Simply changing the mux will not work. 

On the reported x2 link stability issue, I saw you and Brad proved that changing to external refclk shows no improvement. So I suggest we first validate electrical compliance on the x2 link, if join debug with software testing needed, please link me in again. 

regards

Jian 

Basic function test：
1.Set the desired speed to x1 lane, gen1; all boards can pass the test
2.expect x2 lane, gen2, actually x1 lane, gen2, lane0 pass and lane1 failed
3.expect x2 lane, gen2, actually x2 lane, gen1

Check whether there is any problem with PCB design：
1.PCIe loop adds 100R terminal matching resistance, no improvement
2.Use other two boards which has AM5708 or Xilinx A7 etch to test，same result, no improvement
3.Replace the PCIe CLK capacitance of the abnormal board to NEW capacitance, no improvement
4.Exchange the PCIe CLK capacitance of the normal board with the capacitance on the abnormal board, no improvement
5.Replace the BTB connector (which carrys the PCIe circuits) of abnormal board to NEW BTB connector , no improvement
6.Exchange the BTB connector (which carrys the PCIe circuits) of the normal board with the BTB connector of the abnormal board, no improvement
7.Hardware loopback PCIe link, using Xilinx A7 eye diagram test; the eye diagram is better, and the line signal routing quality is no problem

Check whether there is any problem with power supply：
1.Measure the ripple of AM5780’s PCIe power supply, about 18.4mV, which is less than the MAX Vpp 50mV described in the manual

2.Compare the differences of CPU power supply (include sequence and ripple)on normal board and abnormal board, there are not much differences to tell, basically the some
3.Compare the differences of CPU power supply (include sequence and ripple) on abnormal board when PCIe test pass and failed, basically the some
4.Compare the differences of 1V power supply ripple of Xilinx A7 on normal board and abnormal board, basically the some, about 24~30mV
5.Compare the differences of 1V power supply ripple of Xilinx A7 on abnormal board when PCIe test pass and failed, basically the some, about 24~30mV

Check whether there is any problem with the oscillator：
1.Measure the frequency offset of the oscillator, no frequency offse has been observed
2.Compare the differences of the oscillator output on normal board and abnormal board, basically the some
3.Compare the differences of the oscillator output on abnormal board when PCIe test pass and failed, basically the some
4.Replace the oscillator to another bigger and more expensive oscillator which has been use on a mass-produced AM5728 platform, no improvement
5.Measure the waveform of the oscillator output and compare to the oscillator on mass-produced AM5728 platform, basically the some

Check whether there is any problem with Thermal issue：
1.Use the High and Low temperature humidity and heat test chamber to set the test environment temperature to 5℃, no improvement

Check whether there is any problem with AM5708：
1.Interchange the AM5708 CPU of the normal board and the AM5708 CPU of the abnormal board;The AM5708 CPU of the normal board + PCB test of the abnormal board was normal for 150 times; the AM5708 CPU of the abnormal board + PCB test of the normal board failed after 5 tests
2.In summary, the PCIe link training problem currently located may be related to different AM5708 CPUs, and the error probability is relatively high.

Hi, Any update here？