C6745 PLLCTL PLLEN Question

Dennis,

Some things need to be defined more for us (or at least for me), please:

1. we used the spectrum analyzer to sniff the system clock, and then it disappeared
2. ESD shots
3. 400msec (sq wave or 400 low+1.77 high?)  vs.  a weird interval 1.66 second low and 1.77milli-second high

Dennis Nguyen said:

After ESD shots, the system clock disappeared from the spectrum analyzer.

I would ask you whether ESD shots tend to disrupt the logic states and external signals feeding Large Scale Integrated logic CMOS devices like the C6745. I know that we put ESD protection circuitry into our devices to help them survive limited ESD events, but I do not believe that includes detecting that an ESD event has occurred so that a firmware response can be executed.

Dennis Nguyen said:

My thought was the firmware couldn't be running without the system clock.

We can all agree on this statement. although it could depend on which pin you are using to toggle the watchdog timer. If it was a timer output pin and the timer got goofed up, ... but that seems very unlikely. I am sure you are seeing this same response consistently or you would not have asked. Is that the case? That every time you zap it you get this 1.66177 second pulse rate to the WDT?

Dennis Nguyen said:

Is it possible that the DSP got zapped and the PLL switch to a bypass clock even that I set PLLEN to 1?

This also sounds like a very unlikely scenario, because in bypass mode the system clock would probably drop from 300MHz to 25-50MHz depending on what your external oscillator's speed is. It is just as likely that the PLL divider changed or another divider in the clock tree, or even the external oscillator could have changed. But the clock rate change that you are observing seems to be about 1/4 speed to make the high-priority task slow down from 400ms to 1600ms.

Dennis Nguyen said:

Any suggestion for this scenario to reset the DSP?

Since the DSP does not come with a way to detect an ESD event, you would have to detect the clock rate has changed. The easiest that I can think of is to tighten the resolution of your WDT to somewhere between 400ms and 1600ms so the WDT would detect the change and generate a reset to the entire board and not just the DSP.

A harder way would be to find some SYSCLK output or generate a timer output and do constant comparisons with another known clock. But this would require a CPLD or maybe an MSP430 if the signal speeds would work.

Is this what you were looking for?

Regards,
RandyP