can not boot

Daniel Kung

Other Parts Discussed in Thread: OMAP-L138, AM1808

hi，

I have a problem，can not boot。I am custom board。MT47H64M16 -37E (DDR2 ).I think UBL found boot,but can not booting at 0xC1080000.I can read and write ddr2.

OMAP-L138 initialization passed!
Booting TI User Boot Loader
UBL Version: 1.65
UBL Flashtype: NAND
Starting NAND Copy...
Valid magicnum, 0x55424CBB, found in block 0x00000002.
DONE
Jumping to entry point at 0xC1080000.

over 15 years ago

0 jc-ti over 15 years ago

TI__Mastermind 27585 points

How did you flash the UBL and U-boot on your board? Did you get the UBL from the PSP package for OMAP-L138?

Jeff

0 Power Pan over 15 years ago in reply to jc-ti

Expert 1985 points

when printing out the message, it means UBL is loaded ok, found the magic number, means u-boot found, as I know, I just made a customer board work.

my suggest is, if you change the output UART ?

if everything ok, please check the copied bin is correct or not.

set a breakpoint at the end of UBL, and verify the u-boot codes manually before get into the entrypoint

0 Daniel Kung over 15 years ago in reply to jc-ti

Prodigy 245 points

Hi, MY UBL is OMAP-L138_FlashAndBootUtils_2_30.tar.gz and I rewrite the DDR2 timing .

DEVICE_ExternalMemInit(Uint32 ddrphycr, Uint32 sdcr, Uint32 sdtimr, Uint32 sdtimr2, Uint32 sdrcr, Uint32 sdcr2)

DEVICE_ExternalMemInit(0x000000C5, 0x13c622, 0x24494109, 0x4213c722, 0xc0000492, 0x00000000);

now I use DaVinci-PSP-SDK-03.20.00.14,and rewrite the DDR2 timing . I found same problem . DDR2 (MT47H64M16-37E) at 150 MHz

Booting with TI UBL

Device OPP (300MHz, 1.2V)

Booting Catalog Boot Loader

BootMode = NAND

Valid magicnum, 0x55424CBB, found in block 0x00000002.

DONE

I can write and read from DDR2, read==write.I think ddr2 maybe not exact。

0xC1080000 EA000012 E59FF014 E59FF014 E59FF014 E59FF014 E59FF014 E59FF014
0xC108001C E59FF014 C10800A0 C1080100 C1080160 C10801C0 C1080220 C1080280
0xC1080038 C10802E0 DEADBEEF C1080000 C1080000 C10A9E14 C10F14AC E10F0000

   // Config DDR timings
EMIF3A->DDRPHYC1R   = (0x0               << 8)   | // Reserved
                  (0x1               << 7)   | // EXT_STRBEN
                  (0x1               << 6)   | // PWRDNEN
                  (0x0               << 3)   | // Reserved
                  (0x5               << 0);     // RL 0xc5 //ddrphycr;

ddr2

EMIF3A->SDCR        =   sdcr |
                   (0x0               << 27) | // DDR2TERM1
                  (0x0               << 26) | // IBANK_POS
                  (0x0               << 25) | // MSDRAMEN
                  (0x0               << 24) | // DDRDRIVE1
                  (0x0               << 23) | // BOOTUNLOCK
                  (0x0               << 22) | // DDR2DDQS
                  (0x0               << 21) | // DDR2TERM0
                  (0x1               << 20) | // DDR2EN
                  (0x0               << 19) | // DDRDLL_DIS
                  (0x0               << 18) | // DDRDRIVE0
                  (0x1               << 17) | // DDREN
                  (0x1               << 16) | // SDRAMEN
                  (0x1               << 15) | // TIMUNLOCK
                  (0x1               << 14) | // NM
                  (0x0               << 12) | // Reserved
                  (0x3               << 9)   | // CL
                  (0x0               << 7)   | // Reserved
                  (0x2               << 4)   | // IBANK
                  (0x0               << 3)   | // Reserved
                  (0x2               << 0);     // PAGESIZE    // 0x13c622//sdcr | ((0x1 << DEVICE_SDCR_TIMUNLOCK_SHIFT) & DEVICE_SDCR_TIMUNLOCK_MASK);

EMIF3A->SDTIMR    =(((unsigned int) ((127.5 * freq / 1000) - 1)) << 25) | // tRFC    18 10010
                     (((unsigned int) ((15.0 * freq / 1000) - 0.5)) << 22) | // tRP      1
                     (((unsigned int) ((15.0 * freq / 1000) - 0.5)) << 19) | // tRCD    1
                     (((unsigned int) ((15.0 * freq / 1000) - 0.5)) << 16) | // tWR     1
                     (((unsigned int) ((45.0 * freq / 1000) - 0.5)) << 11) | // tRAS     6 110
                     (((unsigned int) ((60.0 * freq / 1000) - 0.5)) << 6) | // tRC     8
                     (((unsigned int) ((10 * freq / 1000)-0.5)) << 3) | // tRRD        1
                     (0 << 2)                                | // Reserved (EMIF3A_SDTIMR1 & 0x4)
                     (((unsigned int) ((7.5 * freq / 1000))) << 0);    // tWTR       1    //24494109                                                   //sdtimr;

EMIF3A->SDTIMR2     = (0 << 31)                           | // Reserved
                      (8 << 27) | // tRASMAX
                     (0x1                                            << 25) | // tXP
                     (0x0                                            << 23) | // tODT (Not supported)
                     (((unsigned int) ((137.5 * freq / 1000) - 1)) << 16) | // tXSNR 19
                                                                (199<< 8)   | // tXSRD (Using Self-Refresh)11000111
                     (((unsigned int) ((7.5 * freq / 1000) - 0.5)) << 5)   | // tRTP (??)1
                     (0x2                                            << 0);     // tCKE   2        // 0x4213c722

0 Daniel Kung over 15 years ago in reply to Daniel Kung

Prodigy 245 points

NOW I FOUND run nandwrite code step by step ,ccsv4 read uboot .bin from PC to ddr2 is not all right.I think problem is that. ddr2 timing is not right

0 jc-ti over 15 years ago in reply to Daniel Kung

TI__Mastermind 27585 points

Run some basic memory tests in CCS to make sure the DDR settings are working. If not, double check to make sure the timings match the datasheet for the memory.

Jeff

0 Daniel Kung over 15 years ago in reply to jc-ti

Prodigy 245 points

I have checked the DDR2 timing ，it match the datasheet .mybe my PCB layout is not well like Hawkboard。

0 jc-ti over 15 years ago in reply to Daniel Kung

TI__Mastermind 27585 points

Daniel, what revision of the Micron memory are you using? Also, are you using full drive strength or reduced drive strength mode? Does your design use terminators?

Jeff

0 Power Pan over 15 years ago in reply to jc-ti

Expert 1985 points

as my experience, timing is not that important but the bank, width register DO affect the boot

don't waste too much time on it, just use standard GEL file to initialize the board by ccs and jtag cable and test DDR, when pass, try to find other problems.

0 xiaoping liu over 14 years ago in reply to Power Pan

Prodigy 80 points

i have encounter the promblem:

AM1808 initialization passed!
Booting TI User Boot Loader
        UBL Version: 1.65
        UBL Flashtype: NAND
Starting NAND Copy...
Valid magicnum, 0x55424CBB, found in block 0x00000006.
   DONE
Jumping to entry point at 0xC1080000.

"use standard GEL file to initialize the board by ccs and jtag cable and test DDR, when pass"

and the ddr work normal.

I see the SDCR,SDRCR,..... value by the emulator, all the revelent parameters are same to device.c (OMAP-L138_FlashAndBootUtils_2_31)

0 xiaoping liu over 14 years ago

Prodigy 80 points

hi,Daniel Kung,do you have resove the promblem???

0 Prabhakar Lad over 14 years ago

Guru 11260 points

hi Daniel,

from where did you build the bootloader for it? even i had the same issue but fixed it.

Best Regards
Prabhakar Lad

0 xiaoping liu over 14 years ago in reply to Prabhakar Lad

Prodigy 80 points

i found the code in OMAP-L138_FlashAndBootUtils_2_31\Common\ubl\src

/***************************************

DEBUG_printString("   DONE");

// Jump to entry point
DEBUG_printString("\r\nJumping to entry point at ");
DEBUG_printHexInt(gEntryPoint);
DEBUG_printString(".\r\n");

UTIL_waitLoop(10000);

// reset the UART peripheral in use
UART_reset(hUartInfo);

******************************************/

is it go to the gEntryPoint??? i haven't found the revelent code