Hello,
I have a custom board based on AM335x and I have been using 2018.01 version of TI u-boot. In my board.c file(which is based on am335x board.c), I have some changes in board_eth_init(bd_t *bis) function. Now, I am in a process of migrating from 2018.01 to 2020.01 and I see board_eth_init function has been removed from board.c file.
Query: which place in 2020.01 substitute functionality which was part of board_eth_init?
To be more specific, these are the changes I have made for custom board related to cpsw:
@@ -805,12 +778,12 @@ static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
- .phy_addr = 0,
+ .phy_addr = 1,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
- .phy_addr = 1,
+ .phy_addr = 3,
},
};
@@ -820,7 +793,7 @@ static struct cpsw_platform_data cpsw_data = {
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
- .slaves = 1,
+ .slaves = 1, // Edwards 4-CPU: If set to 2, the second PHY will be default uboot port
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
@@ -883,23 +856,9 @@ int board_eth_init(bd_t *bis)
}
#ifdef CONFIG_DRIVER_TI_CPSW
- if (board_is_bone() || board_is_bone_lt() ||
- board_is_idk()) {
- writel(MII_MODE_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_MII;
- } else if (board_is_icev2()) {
- writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
- cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
- cpsw_slaves[0].phy_addr = 1;
- cpsw_slaves[1].phy_addr = 3;
- } else {
- writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
- cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
- PHY_INTERFACE_MODE_RGMII;
- }
-
+ writel(MII_MODE_ENABLE, &cdev->miisel);
+ cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+ PHY_INTERFACE_MODE_MII;
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
@@ -907,27 +866,6 @@ int board_eth_init(bd_t *bis)
n += rv;
#endif
- /*
- *
- * CPSW RGMII Internal Delay Mode is not supported in all PVT
- * operating points. So we must set the TX clock delay feature
- * in the AR8051 PHY. Since we only support a single ethernet
- * device in U-Boot, we only do this for the first instance.
- */
-#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
-#define AR8051_PHY_DEBUG_DATA_REG 0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
-#define AR8051_RGMII_TX_CLK_DLY 0x100
-
- if (board_is_evm_sk() || board_is_gp_evm()) {
- const char *devname;
- devname = miiphy_get_current_dev();
-
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
- AR8051_DEBUG_RGMII_CLK_DLY_REG);
- miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
- AR8051_RGMII_TX_CLK_DLY);
- }
#endif
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))I am seeking help in making similar changes for 2020.01 version of u-boot.
Regards,
Raxesh
