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TMS320C6678: NAND Error Management (ECC - EMIF interface)

Part Number: TMS320C6678


Hello,

we have some troubles with the NAND flash on our C6678 DSP board. Time to time some bits flip over and the error correction management seams not to be performant enough to correct it. On the first revision we were using the same NAND flash which is also on the C6678 EVM (NAND512R3A2SZA6F from Numonyx). This combination worked fine without any issues. Unfortunately, they discontinued the flash and therefore we switched to the MT29F1G08ABBEAH4-ITX:E from Micron. One main difference between this two is the minimum required ECC. Numonyx only prescribe 1-bit ECC every 512 bytes, Micron on the other side 4-bit ECC per 528 bytes of data.

According to the TI user guide (sprugz3a) the EMIF16 of the C6678 supports 1-bit ECC calculation for up to 512 Bytes and 4-bit ECC calculation for up to 518 Bytes.

So my main question is, is the MT29F1G08ABBEAH4-ITX:E from Micron compatible the hardware EMIF16 ECC of the C6678? If so, are there some specific modifications necessary (register values,..)? If not, can anyone provide us a list of supported NAND flashes?

 

Thanks for your support,

Kind regards.

  • Bernhard,

    I recommend that you contact Micron or Numonyx to see if they have parts available that have a similar spec to the original Flash that you were using.

    Regards,

    Kyle

  • Hello,

    we did some further investigations and found out that there is maybe an timing issue in your intermediate bootloader (ibl version 1.0.0.17 – nandemif25.c).

    After we added an extra delay of 10µs between the write register (EMIF25_FLASH_CTL_REG) and the read register (EMIF25_FLASH_STATUS_REG) command the ECC worked. Otherwise, the error_value for the correction is always zero and therefore useless.

    Kind regards,

    Bernhard

  • Bernhard,

    I'm glad to hear that you seem to have resolved your issue.  My guess is that there must be subtle differences in timing between the two flash devices.  TI would have done validation on the Flash device on the EVM, so it's possible that we missed the timing hazard that you are highlighting.

    Regards,

    Kyle