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TDA4VM: Running YoloP on TI edge

Mitul Saha
Intellectual 375 points
Part Number: TDA4VM

I would like to run YoloP (https://github.com/hustvl/YOLOP) on TI edge.

When I try to convert a yoloP onnx into TI edge format, I get these errors:-

ONNX operator Div is not suported now.. By passing
ONNX operator Div is not suported now.. By passing
ONNX operator ScatterND is not suported now.. By passing
ONNX operator ScatterND is not suported now.. By passing
ONNX operator ScatterND is not suported now.. By passing
ONNX operator ScatterND is not suported now.. By passing
ONNX operator ScatterND is not suported now.. By passing
ONNX operator ScatterND is not suported now.. By passing

Can someone help me resolve these and anything else needed to run YoloP in TI edge?

Thanks!

  • 0
    TI__Intellectual 2406 points

    Hi,

    Will it be possible to share the onnx model and the corresponding config files that were used for import?

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , The "insert" option here does not seem to work. Maybe because onnx is about 35MB. Maybe I can email it to you? Or any other way I can send it to you?

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    I was able to upload it here:   e2eprivate.ti.com/.../7703 

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    HI Mitul,

    Will you please share the complete link? I could not get the full link from above.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi  Here it is:-  e2eprivate.ti.com/.../7703             (When I hit reply, the system compresses the link, but the embedded link here is preserved)

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    In order to efficiently run this model, there are certain changes that needs to be done in this model as we did in YOLOv5. You can refer to those changes here:

    https://github.com/TexasInstruments/edgeai-yolov5

    Apart from that, you need to specify a prototxt file . You can go through this video as well for more information on model changes and defining prototxt.

    https://training.ti.com/process-efficient-object-detection-using-yolov5-and-tda4x-processors

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi https://training.ti.com/process-efficient-object-detection-using-yolov5-and-tda4x-processors says  "The website encountered an unexpected error. Please try again later.". Could you check? Thanks.

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    You can try again. It's working now.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Thanks ! YoloP is different from Yolov5 - but let me check if the changes for latter can fix the former.

  • 0
    Prodigy 61 points

     

    Best to clone the TI yolo and look at the commits from a0132471 <a0132471@ti.com> upward.
    Basic changes where:
    - Substitute unsupported operations
         -- Uses ReLu instead of  unsupported SiLU
         -- Use simple Conv instead of unsupported Max and slicing in custom Fucus layer.

    - add exports for the bounding box detection layers:  xywh2xyxy_export non_max_suppression_export...
    -add protobuffer

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul, Greg,

    Post-processing for YOLOv5 and the detection part of YOLOP look similar. Hence, I hope those changes will work. 

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks! I am trying the understand the process:- Why do we need to specify anchors etc in the prototxt file? - Why is onnx not enough by itself?

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Here is the new ONNX:- https://e2eprivate.ti.com/magna/magna---ep-automotive/m/shared-documents---file-gallery/7708  Now I have made changes as per https://github.com/TexasInstruments/edgeai-yolov5. But I still get the same complains about "Div" and "ScatterND". Any ideas why? I am still not using prototxt (as I need to figure it out yet) - assuming that is not the cause of this problem.

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    HI Mitul,

    I looked into the model. The model has Hardswish activation. That will result in the division error. That needs to be replaced by ReLU. Once that's done, we can look into the prototxt file.

    Prototxt file is needed here because in many cases the ONNX model may not contain the anchor information.  

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks - sure letme remove hardswish. BTW what tool / means did you use to see hardswish? I am using netron to visualize onnx and it does not show hardswish for some reason.

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

     I am using netron as well. The set of operation looked like hardswish. It showed hswish as a set of operations as well:

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks! Here is the new ONNX (after removing hardswish), TIDL config file, and TIDL conversion log (has all errors in it):- https://e2eprivate.ti.com/magna/magna---ep-automotive/m/shared-documents---file-gallery/7710 . Please let me know what went wrong. Thanks.

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    The model doesn't have any hswish and I was able to export it without any error. Can you please confirm the following:

    • Is this a trained model as I am not getting any valid detection.
    • Can you please crosscheck the anchor dimensions? I have taken them from the onnx model and updated the prototxt. Please check the attached prototxt.
    • I am attaching the import config that I used. Please try at your place once and let me know if it works.
    • Can you try to run onnxsimplifier on the model to simplify the model and also have shape information at each node.

    Regards, Debapriya

    yolop_640_debapriya.zip

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks a lot! Let me get back to you ... Meanwhile: what does it precisely mean to "have shape information at each node"? Thanks!

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    You can check this model in the link below. It has shape of all tensors at each node of the model.

    https://github.com/TexasInstruments/edgeai-yolov5/blob/master/pretrained_models/models/yolov5s6_640_ti_lite/weights/yolov5s6_640_ti_lite_37p4_56p0.onnx.link

    This will come once you run onnx simplifier on the existing model.  

    I have one more question :

    • I could not run the shared model in ONNXRunime. Let me know if you are able to run it at your place, 

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Let me get back to you with answers to all your questions. Meanwhile:- Yes this model is from from first few iterations - the training is still running. The goal of this exercise was to ensure this model "runs" on TI and to also estimate inference time. Ok, so I will do "onnx simplify" to satisfy your requirement - "have shape information at each node". When you say "I could not run the shared model in ONNXRunime", did you mean you did not see any detection, or it crashed or something (specifically what happened)?

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    I am getting this error while initializing the onnxrt session:

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks! Let me check. I also need to get back to you with answers about other questions. Meanwhile: you mentioned you did not see any detections from inference -- what inference time did you observe? (assuming it is for TDA4VM)

  • 0 in reply to Mitul Saha
    Intellectual 375 points

    Hi , Thanks for the new config file and prototxt. When I run model conversion here, I get these errors:-

    ...

    Error in reading /testvecs/models/yolop/yolop_640.txt_stats_tool_out.bin_ti_lindau_000020.bmp_000001.txt, /testvecs/models/yolop/yolop_640.txt_stats_tool_out.bin_ti_lindau_000020.bmp_000001.txt

    ...

    substitute string tidl_net_ not found

    ...

    ERROR: TIDL_E_QUANT_STATS_NOT_AVAILABLE] tidl_quant_stats_tool.out fails to collect dynamic range. Please look into quant stats log. This model will get fault on target.
    ****************************************************
    ** 8 WARNINGS 1 ERRORS **
    ****************************************************

    What am i missing? Thanks!

  • 0 in reply to Mitul Saha
    Intellectual 375 points

    Hi , About the onnxruntime issue, seems like your issue is same as discussed here:- https://github.com/hustvl/YOLOP/issues/110 It seems one person there claims to not have issue if "right environment is used". I am trying to figure it out here. If you have any ideas, then feel free to let us know. 

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    HI Mitul,

    • Enable line#21 in the import config. 
    • Please ensure that "inData" path is correct.
    • Regarding the ONNXRT, it is not critical. I wanted to compare TIDL output with ONNXRT. Hence,  I needed it. I will check the github issue that you mentioned.
    • I have run the model in PC emulation. Hence, I don't have the exact latency numbers. Since, this model is similar to YOLOv5, it will be close to 8mS for complete 8 bit model.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Which import config file are you referring to? Where is it? Also size of testvecs/models/yolop/yolop_640.txt_stats_tool_out.bin_ti_lindau_000020.bmp_000001.txt is 0 - maybe that is why it is saying "Error in reading". Thanks!

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

     I was referring import config that is part of the previous attachment yolop_640_debapriya.zip. 

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , I have turned line#21 now. But I still get those errors. I notice size of testvecs/models/yolop/yolop_640.txt_stats_tool_out.bin_ti_lindau_000020.bmp_000001.txt is 0. Any ideas?

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    HI Mitul,

    Please check if  inData points to a valid set of images? 

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi Here is what I have:-

    inData = "/home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/config/detection_list.txt"

    cat /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/config/detection_list.txt
    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/ti_lindau_000020.bmp

    ls -l /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/ti_lindau_000020.bmp
    -rw-r--r-- 1 msaha msaha 1572918 Feb 3 12:00 /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/ti_lindau_000020.bmp

    So it seems like it is pointing to right image?

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    Can you try changing numFrames = 1. There is a single image in the list and numFrames is set to 10. 

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks that helps. Now I get these issues (other output lines look fines):-

    #    0 . .. T   10368.47  .... ..... ...Segmentation fault (core dumped)

    substitute string tidl_net_ not found

    **          8 WARNINGS          0 ERRORS          **

    What do you say? 

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    Can you add some more images in the detection list. I would suggest to add five images and set numFrames = 5.

    Please share the entire import  trace as well.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks. So I now use 5 same images (I can try to use different ones if you want me to). I get this:-

    ./out/tidl_model_import.out /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/config/import/yolop_640.txt


    TIDL Meta PipeLine (Proto) File : /home/msaha/software/yolop_ti/weights/yolop_640_ti_lite_metaarch.prototxt
    yolo_v3
    yolo_v3
    ONNX Model (Proto) File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop-640-640.o11.onnx
    TIDL Network File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/tidl_yolop-640-640.bin
    TIDL IO Info File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/tidl_io_yolop-640-640_
    Current ONNX OpSet Version : 11

    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop_640.txt.qunat_stats_config.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 13591.66 .... ..... ... .... .....
    # 1 . .. T 13615.46 .... ..... ... .... .....
    # 2 . .. T 14007.64 .... ..... ... .... .....
    # 3 . .. T 14087.56 .... ..... ... .... .....
    # 4 . .. T 14383.46 .... ..... ... .... .....
    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop_640.txt.qunat_stats_config.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 10535.81 .... ..... ...Segmentation fault (core dumped)



    ***************** Calibration iteration number 0 completed ************************

    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    substitute string tidl_net_ not found
    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/utils/tidlModelGraphviz/out/tidl_graphVisualiser.out: error while loading shared libraries: libcgraph.so.6: cannot open shared object file: No such file or directory
    INFORMATION: [TIDL_ResizeLayer] Resize_107 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_125 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_620 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_661 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_637 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_678 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_654 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_695 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    ****************************************************
    ** 8 WARNINGS 0 ERRORS **
    ****************************************************

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    Thanks for sharing the trace. Please try using five different images.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Sure. I now used these five:-

    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/ti_lindau_000020.bmp
    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/ti_lindau_640x640.bmp
    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/ti_lindau_I00000.bmp
    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/0000000272.bmp
    /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/input/0000003436.bmp

    I still get same output.

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    I am trying with the attached images and it works fine. Can you please give it a try.

    sample_images.zip

    If possible, please share the images that you are using. I can also give it a try.

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi  I still get the same output with your images. BTW, did you notice this error: "/home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/utils/tidlModelGraphviz/out/tidl_graphVisualiser.out: error while loading shared libraries: libcgraph.so.6: cannot open shared object file: No such file or directory" ?

  • 0 in reply to Mitul Saha
    Intellectual 375 points

    Hi I was able to resolve above missing library issue via  https://stackoverflow.com/questions/40528048/pip-install-pygraphviz-no-package-libcgraph-found . But I still get that Segmentation fault and "substitute string tidl_net_ not found".

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    This error "substitute string tidl_net_ not found". is fine. 

    For segmentation fault, can you disable the line  " outDataNamesList = "1533, 1595" " and try running import. This will consider the detection part of the model only.  Want to check if the detection part is working correctly.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks that may have worked. This is the output now:-

    ./out/tidl_model_import.out /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/config/import/yolop_640.txt
    TIDL Meta PipeLine (Proto) File : /home/msaha/software/yolop_ti/weights/yolop_640_ti_lite_metaarch.prototxt
    yolo_v3
    yolo_v3
    ONNX Model (Proto) File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop-640-640.o11.onnx
    TIDL Network File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/tidl_yolop-640-640.bin
    TIDL IO Info File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/tidl_io_yolop-640-640_
    Current ONNX OpSet Version : 11

    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop_640.txt.qunat_stats_config.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 7266.44 .... ..... ... .... .....
    # 1 . .. T 7465.84 .... ..... ... .... .....
    # 2 . .. T 7550.44 .... ..... ... .... .....
    # 3 . .. T 7572.29 .... ..... ... .... .....
    # 4 . .. T 7401.64 .... ..... ... .... .....
    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop_640.txt.qunat_stats_config.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 5976.82 .... ..... ... .... .....
    # 1 . .. T 5929.61 .... ..... ... .... .....
    # 2 . .. T 5898.54 .... ..... ... .... .....
    # 3 . .. T 5866.30 .... ..... ... .... .....
    # 4 . .. T 5789.43 .... ..... ... .... .....


    ***************** Calibration iteration number 0 completed ************************

    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    substitute string tidl_net_ not found
    INFORMATION: [TIDL_ResizeLayer] Resize_107 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_125 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    ****************************************************
    ** 2 WARNINGS 0 ERRORS **
    ****************************************************

    So is everything fine now?

    Also any ideas how to do inference timing (and memory usage) for the edge device?

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    That's great. So the object detection part of the model is working fine. Now, you can enable that line  " outDataNamesList = "1533, 1595" "  again. 

    Now, disable the line "postProcType = 2" . With this, you should be able to import the entire model. Let me know if that worked.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , Thanks! So now this is the output:-

    ./out/tidl_model_import.out /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/config/import/yolop_640.txt
    TIDL Meta PipeLine (Proto) File : /home/msaha/software/yolop_ti/weights/yolop_640_ti_lite_metaarch.prototxt
    yolo_v3
    yolo_v3
    ONNX Model (Proto) File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop-640-640.o11.onnx
    TIDL Network File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/tidl_yolop-640-640.bin
    TIDL IO Info File : /home/msaha/software/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/tidl_io_yolop-640-640_
    Current ONNX OpSet Version : 11

    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop_640.txt.qunat_stats_config.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 13767.81 .... ..... ... .... .....
    # 1 . .. T 13569.89 .... ..... ... .... .....
    # 2 . .. T 13568.30 .... ..... ... .... .....
    # 3 . .. T 13731.77 .... ..... ... .... .....
    # 4 . .. T 13795.71 .... ..... ... .... .....
    ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~

    Processing config file #0 : /home/msaha/Downloads/ti-processor-sdk-rtos-j721e-evm-08_01_00_13/tidl_j7_08_01_00_05/ti_dl/test/testvecs/models/yolop/yolop_640.txt.qunat_stats_config.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 10082.30 .... ..... ... .... .....
    # 1 . .. T 10034.68 .... ..... ... .... .....
    # 2 . .. T 10071.12 .... ..... ... .... .....
    # 3 . .. T 10069.01 .... ..... ... .... .....
    # 4 . .. T 10013.02 .... ..... ... .... .....


    ***************** Calibration iteration number 0 completed ************************

    ------------------ Network Compiler Traces -----------------------------
    successful Memory allocation
    substitute string tidl_net_ not found
    INFORMATION: [TIDL_ResizeLayer] Resize_107 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_125 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_620 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_661 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_637 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_678 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_654 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    INFORMATION: [TIDL_ResizeLayer] Resize_695 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize.
    ****************************************************
    ** 8 WARNINGS 0 ERRORS **
    ****************************************************

    Does it look good?  BTW the model is supposed to have 3 output heads:- detections, drivable area, lane lines:- https://github.com/hustvl/YOLOP I hope are three are working.

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    Hi Mitul,

    This looks good. All outputs are working. You can measure the latency on device like any other model. Let me know if you see any specific challenge for this model.

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Thanks a lot ! I will definitely let you know of any more issues. Thanks!

  • 0 in reply to Mitul Saha
    Intellectual 375 points

    Hi I am trying to run inference on this model for TI. I am using this interface: https://dev.ti.com/tidl_0059fdae4058a5e56db1d34cf2c7a3b6/notebooks/notebooks/custom-model-onnx.ipynb I do not see here a way to start with TI model that we generated here. Or to use the the config file you gave me. Any ideas? Thanks!

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , When I run inference via steps in software-dl.ti.com/.../md_tidl_sample_test.html

    I get these results:-

    Processing config file #0 : /home/msaha/yolop_ti/weights/yolop_640_infer.txt
    ----------------------- TIDL Process with REF_ONLY FLOW ------------------------

    # 0 . .. T 10165.74 .... ..... ... .... .....
    # 1 . .. T 10097.46 .... ..... ... .... .....
    # 2 . .. T 10149.59 .... ..... ... .... .....
    # 3 . .. T 10083.30 .... ..... ... .... .....
    # 4 . .. T 10159.40 .... ..... ... .... .....

    What do these number mean? What is the final inference time? What is the memory usage? This was run on SDK installed in desktop. Is the inference time obtained in SDK installed in desktop same as if it was run on actual TI Board?

    Thanks!

  • 0 in reply to Mitul Saha
    TI__Intellectual 2406 points

    HI Mitul,

    These are the time it took to run on PC. You need to run in on EVM to get the actual numbers.  Steps to run on EVM are in the same page that you have referred.

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_01_00_13/exports/docs/tidl_j7_08_01_00_05/ti_dl/docs/user_guide_html/md_tidl_sample_test.html

    Regards, Debapriya

  • 0 in reply to Debapriya Maji
    Intellectual 375 points

    Hi , I think by EVM you are referring to https://www.ti.com/product/TDA4VM device. We do not have it yet. Hence we have to run it on cloud:- https://dev.ti.com/tidl_0059fdae4058a5e56db1d34cf2c7a3b6/notebooks/notebooks/custom-model-onnx.ipynb - I do not see here a way to start with TI model that we generated here. Or to use the the config file you gave me. Any ideas? Thanks!