AM5728: McSPI EDMA no RX/TX event trigger to ESR Register, SPI_transfer blocking

Hello,

I am making a new post with a more specific issue. My original post can be found here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1088012/am5728-spi-edma3-configuration/4032509?tisearch=e2e-sitesearch&keymatch=%20user%3A415723#4032509

I am using ti-processor-sdk-rtos-am57xx-evm-06.01.00.08

https://software-dl.ti.com/processor-sdk-rtos/esd/AM57X/06_01_00_08/index_FDS.html

I am trying to implement (E)DMA on TI's RTOS in the DSP. I have based my code on the DMA examples in "packages/ti/drv/spi/example/"

I have successfully enabled and configured the McSPI2 Interface (2nd interface) and can transmit data in POLLING mode (but NOT in BLOCKING mode).

I then configure EDMA and upon calling SPI_transfer(), the code blocks in an idle loop waiting for the DMA read/write to complete, which never occurs.

I am able to manually trigger the DMA read/write request by writing to bits 10 and 11 of the ESR(high) register myself, which allows the code to continue and no longer block on SPI_transfer()

Bits 10 and 11 correspond to EDMA DMA_EDMA_DREQ_42 (McSPI2 transmit request channel 0)  and DMA_EDMA_DREQ_43 (McSPI2 receive request channel 0) respectively

Table 16-89. EDMA Default Request Mapping from the TRM

Table 16-205. EDMA_TPCC_ESRH

Relevant Code:

#include <xdc/runtime/System.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <string.h>
#include <dss.h>
#include <stdlib.h>
#include <stdio.h>
#include <byteorder.h>

/* SPI Header files */
#include <ti/drv/spi/SPI.h>
#include <ti/drv/spi/soc/SPI_soc.h>
#include <ti/drv/spi/soc/SPI_v1.h>
#include <ti/drv/spi/test/src/SPI_log.h>
#include <ti/drv/spi/test/src/SPI_test.h>

#ifdef SPI_DMA_ENABLE
/* EDMA3 Header files */
#include <ti/sdo/edma3/drv/edma3_drv.h>
#include <ti/sdo/edma3/rm/edma3_rm.h>
#include <ti/sdo/edma3/rm/sample/bios6_edma3_rm_sample.h>

#include <ti/osal/CacheP.h>
#endif

#include <circular_buffer.h>

SPI_Handle globalSpiHandle;
#ifdef SPI_DMA_ENABLE    
EDMA3_DRV_Handle gEdmaHandle = NULL;
EDMA3_DRV_Handle initGlobalEDMA3Handle(uint32_t instance, EDMA3_DRV_Result *errorCode);
#endif

#ifdef SPI_DMA_ENABLE
extern EDMA3_DRV_GblConfigParams edma3GblCfgParams[];
static void enableEDMAHwEvent(uint32_t edmaNum, uint32_t eventNo) {
    edma3GblCfgParams[edmaNum].dmaChannelHwEvtMap[eventNo/32] |=
        (1 << (eventNo%32));
}
#endif

int dss_init(void) {
    SPI_Transaction transaction;
    uint8_t tx_data[MAX_SPI_XFER_SIZE];
    uint8_t rx_data[MAX_SPI_XFER_SIZE];
    uint16_t addr;
#ifdef SPI_DMA_ENABLE
    EDMA3_DRV_Result edmaResult = EDMA3_DRV_E_INVALID_PARAM;
#endif
    int interface;
    SPI_Params params;
    SPI_v1_HWAttrs spi_cfg;
    bool retVal;
    CSL_l4per_cm_core_componentRegs *l4PerCmReg =
        (CSL_l4per_cm_core_componentRegs *) CSL_MPU_L4PER_CM_CORE_REGS;

#ifdef SPI_DMA_ENABLE

    /* Enable MSPI1 (0 index) EDMA HW Events */
    enableEDMAHwEvent(1, CSL_EDMA3_CHA0_MCSPI1_RX);
    enableEDMAHwEvent(1, CSL_EDMA3_CHA0_MCSPI1_TX);
    
    gEdmaHandle = initGlobalEDMA3Handle(1, &edmaResult);
    if (edmaResult != EDMA3_DRV_SOK)
    {
        /* Report EDMA Error */
        dss_err("%s: EDMA driver initialization FAIL\n", __func__);
        return -1;
    }
#endif
        /* enable MCSPI2 (1 index) Clock */
    CSL_FINST(l4PerCmReg->CM_L4PER_MCSPI2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_MODULEMODE, ENABLE);

    while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(l4PerCmReg->CM_L4PER_MCSPI2_CLKCTRL_REG,
        L4PER_CM_CORE_COMPONENT_CM_L4PER_MCSPI2_CLKCTRL_REG_IDLEST));

    /* Get the default SPI init configurations */
    SPI_socGetInitCfg(1, &spi_cfg);

    /* Modify the default SPI configurations if necessary */
    spi_cfg.chnCfg[spi_cfg.chNum].dataLineCommMode = MCSPI_DATA_LINE_COMM_MODE_1;
    spi_cfg.enableIntr = FALSE;
#ifdef SPI_DMA_ENABLE
    /* Set the DMA related init config */
    spi_cfg.edmaHandle = gEdmaHandle;
    spi_cfg.dmaMode    = TRUE;
    spi_cfg.enableIntr = FALSE;
#endif
    /* Set the default SPI init configurations */
    SPI_socSetInitCfg(1, &spi_cfg);
   
    SPI_init();
    
    /* get default params for now */
    SPI_Params_init(&params);
    params.bitRate  = 16000000; /* SPI bit rate in Hz */
    params.dataSize = 8;        /* SPI data frame size in bits */

    globalSpiHandle = SPI_open(1, &params);

    if(globalSpiHandle == NULL)
    {
        printf("\nError opening SPI driver\n");
        return -1;
    }
 
    tx_data[0] = 0x4;

#ifdef SPI_DMA_ENABLE
    CacheP_wbInv((void *)tx_data, (int32_t)sizeof(tx_data));
    CacheP_wbInv((void *)rx_data, (int32_t)sizeof(rx_data));
#endif
    transaction.txBuf = &tx_data;
    transaction.rxBuf = &rx_data;
    transaction.count = 1;

    SPI_transfer(globalSpiHandle, &transaction);

    return 0;
}

Why are the RX/TX events for McSPI2 (2nd interface) Channel 0 not being triggered automatically via the EDMA?