• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 712 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6412: AM64x Debug Infrastructure

Walter Stoll
Intellectual 490 points
Part Number: AM6412

Hi team,

The "On-Chip Debug" section of the "AM64x /AM243x Processors Silicon Revision 1.0" technical reference manual is currently empty. Where can we obtain these information ? The following items regarding JTAG debugging and trace are of particular interest:

  • CoreSight implementation
    • Is a ETB available ? If yes how deep is  it ?
    • Is a STM available ?
    • Is a TPIU available ?
    • Is it possible to direct trace data to DDR SDRAM or to RAM located on a PCIe device ?
  • Is it possible to halt the periphery (e.g. timers) upon entry into debug mode ?
  • Is it possible to disable the watchdogs by menas of the JTAG debugger ?

 

  • 0
    TI__Guru 62835 points

    I was told the next revision of the AM64x TRM will contain a Debug subsystem chapter. However, I was not able to get a firm date when a new revision of the TRM will be available.

    Meanwhile, I will try to find answers to your questions or re-assign your post to someone that is able to answer your questions.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Guru 62835 points

    I inserted answers to your questions below.

    • CoreSight implementation
      • Is a ETB available ? If yes how deep is  it ? >> AM64x includes a TBR (Trace Buffer Router) with 64KB of storage.  The TBR supports operation as a buffer (i.e. same as ETB, including programmers model) or as a “system bridge” (where DMAs or CPUs are responsible for offloading trace data)
      • Is a STM available ? >> Yes
      • Is a TPIU available ? >> Yes
      • Is it possible to direct trace data to DDR SDRAM or to RAM located on a PCIe device ? >> Using the “system bridge mode”  (see response to ETB question above) it would be possible, via DMA or CPU assistance, to offload trace data to an address mapped location
    • Is it possible to halt the periphery (e.g. timers) upon entry into debug mode ? >> Peripherals that support suspend (timers generally do) can be halted when an associated processor enters debug mode
    • Is it possible to disable the watchdogs by menas of the JTAG debugger ? >> Watchdogs can be disabled using the “halt the peripheral” feature from the previous question.  JTAG debuggers would also have the ability to make accesses to SOC address space and so could also interact with watchdog that way

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 490 points

    Hello Paul

    Thanks for the response. This is enough information for me so far. I hope all this will be documented in the TRM soon. For me the debug section in a TRM is really important.

    Regards

    Walter

  • 0 in reply to Walter Stoll
    TI__Guru 62835 points

    We do not find many customers asking detailed questions about the debug subsystem. Can you provide more information as to why this content is important to you? 

  • +1 in reply to peaves
    Intellectual 490 points

    We think that any kind of analysis means is important to know when it comes to bug analysis of such complex systems as Linux platforms are.

    We use Lauterbach for JTAG debugging. This is because we don't want to maintain the IDEs of all different vendores we use to build our Linux based platforms. This debugger requires some knowledge of the debug infrastructure if we want to take full advantage of its features.

  • 0 in reply to Walter Stoll
    TI__Guru 62835 points

    Thanks, I'll pass along your comments to the guy that develops our debug subsystem content for the TRM.

    Regards,
    Paul