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AM4378: MCASP_PFUNC register setting

Kanae
Mastermind 9865 points
Part Number: AM4378

Hi Support Team,

In the MCASP_PFUNC register, it seems that it is possible to set
whether Pin fuciton is McASP or GPIO as shown below,
but how is this setting related to the mode setting of Control Module register
setting CTRL_CONF_each pin name?

For example, if I want to use pin MCASP0_AXR1 as GPIO,
do I need to set B[3:0]=0x7 mode7 in CTRL_CONF_MCASP0_AXR1 and B[3:0]=0x1 in MCASP_PFUNC?

Or if I set B[3:0]=0x7 in CTRL_CONF_MCASP0_AXR1,
will this setting take priority and the device will function as a GPIO regardless of the MCASP_PFUNC setting?


Best regards,
Kanae

  • 0
    TI__Mastermind 29550 points

    Hi Kanae,

    The CTRL_CONF_MCASP* registers control pin multiplexing - the least significant 4 bits (*_MMODE) selects the muxmode - this selects which signal appears on the pin.

    If the muxmode selects a signal that goes to a McASP, then inside the McASP peripheral the respective signal can be configured and controlled as a "McASP" GPIO with MCASP_PFUNC, MCASP_PDIR, MCASP_PDOUT, MCASP_PDIN, MCASP_PDCLK registers.

    If the signal goes to GPIOx_y, then the respective GPIO can be controlled with the registers assigned to the respective GPIO module and pin.

    Refer to TRM Table 2-3. L4_PER Peripheral Memory Map for the base addresses of each GPIO bank. Each bank shares the same registers at same offsets, described in TRM Table 28-5. GPIO REGISTERS

    For example GPIO3 group of regs starts at 0x481A_E000 and ends at 0x481A_EFFF
    The GPIO3 instance of GPIO_DATAOUT exists at 0x481A_E13C.

    The datasheet Tabe 4-10 shows you all of the signals available on each pin:

    Regards,
    Mark

  • 0 in reply to Mark M
    Mastermind 9865 points

    Hi Mark,

    Thank you for your reply.
    Please let me check just to be sure.

    Is your answer explaining that MCASP0_AXR1 pi can be used as a GPIO
    when it is used as MCASP0_AXR1 mode?

    The point I would like to confirm is that when using MCASP0_AXR1 pin as GPIO mode,
    If B [3:0] = 0x7 is set in CTRL_CONF_MCASP0_AXR1, this setting takes precedence
    and the device functions as a GPIO without considering the MCASP_PFUNC register setting.
    It is possible to set the MCASP_PFUNC register with the value B [3:0] = 0x0 after reset.
    Is this understanding correct?

    Best regards,
    Kanae

  • 0 in reply to Kanae
    Mastermind 9865 points

    Hi Mark,

    I would like to have your reply. 
    Please let me check just to be sure.

    Is my understanding correct?

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Mastermind 29550 points

    Hi Kanae,

    Yes. Your understanding is correct - If Bits [3:0] = 0x7 is set in CTRL_CONF_MCASP0_AXR1, this setting takes precedence
    and the device functions as a GPIO without considering the MCASP_PFUNC register setting.

    Regards,
    Mark

  • 0 in reply to Mark M
    Mastermind 9865 points

    Hi Mark,

    Thank you for your reply.
    I will share it with my customer.

    Best regards,
    Kanae