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Original question:

TDA4VM: tidl import size error

TDA4VM: TDA4VM: tidl import size error

Taisuke Okabe
Prodigy 50 points

Part Number: TDA4VM

Hello all,

I have same problem with https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1065342/tda4vm-tidl-import-size-error?tisearch=e2e-sitesearch&keymatch=tda4vm%2520tidl%2520import#

How should I solve this? I tried to change some settings of import, but it cause no effect to result.

Problem :  Output of Imported network is [1,36,95,63]  but correct is  [1,36,96,64] .

Linux SDK :  08.00.00.08 (12 Aug 2021)

RTOS SDK : 08.00.00.12 

  • 0
    Prodigy 50 points

    Important information was missing. I tried to convert from Caffe to TIDL and wrong converting was happened after pooling layer.

  • 0 in reply to Taisuke Okabe
    TI__Mastermind 22145 points

    Can you share steps to re-produce this issue (caffe file and related configurations)

  • 0 in reply to kumar.desappan
    Prodigy 50 points

    Thank you for your support,

    I found Pooling Layer generate irregular size layer as shown as below.

    Of course this structure does not occur in Caffe.

    By the way, This issue has not be solved when PC emulation mode and "numParamBits" is 32.

    - Import Configurations

    modelType = 0
    inputNetFile = "../../test/testvecs/models/public/caffe/mymodel/model.prototxt"
    inputParamsFile = "../../test/testvecs/models/public/caffe/mymodel/model.bin"
    outputNetFile = "../../test/testvecs/config/tidl_models/caffe/mymodel.bin"
    outputParamsFile = "../../test/testvecs/config/tidl_models/caffe/mymodel_"
    inMean = 123.675 116.28 103.53
    inDataFormat = 1
    inDataNorm = 1
    inScale = 1 1 1
    resizeWidth = 768
    resizeHeight = 512
    inWidth = 768
    inHeight = 512
    inNumChannels = 3
    #numParamBits = 32
    inData = "../../test/testvecs/config/detection_list.txt"
    postProcType = 0

    - netLog

        2|TIDL_PoolingLayer             |352                                               |     0|     1|     1|  1   x   x   x   x   x   x   x |  2       |       1        3      512      768 |       1        3      255      383 |   2636955 |

    ------------

       19|TIDL_PoolingLayer             |386                                               |     0|     1|     1| 18   x   x   x   x   x   x   x | 19       |       1      128      128      192 |       1      128       63       95 |   6894720 |

  • 0 in reply to Taisuke Okabe
    TI__Mastermind 22145 points

    Please share the pooling layer Properties to re-produce this issue like - Pooling type, Kernel size, stride size, pad etc

  • 0 in reply to kumar.desappan
    Prodigy 50 points

    This problem has been solved when I changed the "ceil_mode" of prototext.