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EVMK2G: NMI assertion problem

Graziano Rufolo
Intellectual 445 points

Part Number: EVMK2G

Dear experts,

for my work I am developping a bare metal code on the evaluation board EVMK2G that is loaded in the DSP C66x by means of the on-board debugger TI XDS2xxx.

I downloaded the ti-processor-sdk-rtos-k2g-evm-06.03.00.106-Windows-x86-Install.exe and I installed CCS10.2

 

Currently, I need to implement a NMI ISR, but my code does not work.

Here below the code I have written.

 

NRP = &isrNMI; //To write the ISR NMI address within the Nonmaskable Interrupt Return Pointer Register

 

// INTC initialization

gContext.numEvtEntries = (Uint16)C66X_COREPAC_EVENT_CNT;

gContext.eventhandlerRecord = gEventRecord;

(void)CSL_intcInit(&gContext);

 

(void)CSL_intcGlobalNmiEnable();  // To enable global NMI

 

// Next instructions unlock the KICK protecion of MMR

HW_WR_REG32((CSL_BOOT_CFG_REGS + CSL_BOOTCFG_KICK0 ),0x83e70b13);

HW_WR_REG32((CSL_BOOT_CFG_REGS + CSL_BOOTCFG_KICK1 ),0x95a4f1e0);

 

HW_WR_REG32((CSL_BOOT_CFG_REGS + CSL_BOOTCFG_NMIGR0 ),1); // To write ‘1’ within the NMI generation core 0 register

 

By means of the on-board debugger TI XDS2xxx I succesfully verified the setting of NMIE bit within the IER. However I can not verify the status of CSL_BOOTCFG_KICK0, CSL_BOOTCFG_KICK1 and CSL_BOOTCFG_NMIGR0 because in according with the TMR, the read operation returns always 0.

 

However, the ISR NMI is never triggered.

Please, could you tell me what is wrong in my code?

 

Best regards,

Graziano

  • 0
    TI__Guru 58785 points

    Hello Graziano,

    I'm sorry, but TI has stopped supporting TI-RTOS based and bare-metal SW development for K2G. Please refer to the announcement.

    Regards,

    Jianzhong

  • 0 in reply to Jianzhong Xu
    Intellectual 366 points

    Hi Graziano,

    I think the problem lies within the following instruction:

    Graziano Rufolo said:
    NRP = &isrNMI;

    Specifically, in accordance with the Texas Instruments TMS320C6000 Series Reference Manual, "although you can write a value to NRP, any subsequent interrupt processing may overwrite that value".

    Therefore, if no TI expert helps you with a more valuable feedback, I suggest you to write the address of your ISR directly within the INTC vector table.

    CSL_intcCpuIntrTable.nmiIsr = address of your NMI ISR;

    It should work!

     

    Best regards,

    Benito

  • 0 in reply to Benito Carotenuto
    Intellectual 445 points

    Dear Benito,

    thank you for your feedback.

    Following your suggestion, I succesfully programmed the NMI.

     

    Here below my code snippet that programs NMI :

     

         gContext.numEvtEntries = (Uint16)C66X_COREPAC_EVENT_CNT;

         gContext.eventhandlerRecord = gEventRecord;

         (void)CSL_intcInit(&gContext);

         (void)CSL_intcGlobalNmiEnable(); // This API enables global NMI

     

         CSL_intcCpuIntrTable.nmiIsr = addrIsr; // The address of the ISR is written within the vector table

     

        // Next instructions unlock the KICK protection of the memory mapped registers

        HW_WR_REG32((CSL_BOOT_CFG_REGS + CSL_BOOTCFG_KICK0 ),0x83E70B13);

        HW_WR_REG32((CSL_BOOT_CFG_REGS + CSL_BOOTCFG_KICK1 ),0x95A4f1E0);

     

        //BOOTCFG_NMIGR0 register generates NMI event to C66x core. Writing a 1 to the NMIG field generates an NMI pulse

        HW_WR_REG32((CSL_BOOT_CFG_REGS + CSL_BOOTCFG_NMIGR0), 1);

     

    However, the NMI does not nest the maskable interrupt. ……And yet, according to TMR “an NMI can interrupt a maskable interrupt, but neither an NMI nor a maskable interrupt can interrupt an NMI.”

    Why does this happen?

     

    Graziano