AM6442: Internal RAM isolation in runtime

There are two parts to the memory mapping and dividing the internal SRAM. One is the memory map and the performance independence (purpose of the diagram you attached), second is protecting from unwanted accesses.

For the first part, the 8 regions of the 2MB are statically mapped to 256kB regions or banks. This is shown in the TRM at page 39 section "Table 2-1. MAIN Domain Memory Map" has:

Using these regions from various cores is up to the user and can be dynamic. So for example region 0x070000000 to 0x07003FFFF could be used as shared during boot and initialization, but perhaps assigned to be solely used by one R5 later. The physically address of each 256kB region is static, and the performance partitioning is achieved by simple choosing which core and when uses what area/region.

The second part of enforcing that there are no unintended accesses would be based on the combination of MMU configuration for A53 (typically done with Linux), MPU+RAT for each R5, and optionally the firewalls (3.3.2 Interconnect Firewalls in the TRM).

  Pekka