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Original question:

TMS320C6678: Not receiving a combined interrupt when specified events occur

TMS320C6678: CBA 3.0 Specification

Steven Sherbert
Intellectual 580 points

Part Number: TMS320C6678

Hi, KeyStone Architecture Telecom Serial Interface Port (TSIP) User Guide references the CBA 3.0 Specification on page 2-13. 

Is there a link to this specification?

I am receiving errors that reference the spec.

-Steve

  • 0
    TI__Expert 4314 points

    Hi Steve,

    CBA3.0 is a TI Common Bus Architecture used in Keystone devices. The specifications has not been released publicly (Though they have mentioned CBA3.0 compliant for TSIP and CBA3.1 compliant for Hyperlink). Only the CBA architecture is available (CBA).

    "Texas Instruments developed the common bus architecture (CBA) as a convenient and scalable method of connecting the blocks in a system-on-chip (SoC) without changing the modules themselves. CBA provides up to 16,000 M-bytes/s (MBps) per interface @ 500 MHz (using a 256-bit data bus) and supports data paths with 8-, 16-, 32-, 64-,128- or 256-bit data, depending on a trade-off between power, area, and performance.

    The CBA also:

    • Allows both pipelined burst read and write operations and non-pipelined transfers
    • Provides continuous back-to-back transactions, multiple masters, and background master arbitration
    • Supports slave-inserted (but not master-inserted) wait states

    CBA is a internal communcation between the peripherals in the Keystone devices. CBA can also extended between two keystone devices (whcih can be implemented by Hyperlink).

    Thanks,

    Rajarajan U

  • 0 in reply to Rajarajan Uthayakumar
    Intellectual 580 points

    Hi Rajarajan U,

    I have ported an existing 6472 TSIP driver to run on the 667x platform.  The driver configures the TSIP identically to that of the TSIP_evmc6678_c66exampleProject.  The TSIP_evmc6678_c66exampleProject project runs without error. 

    After TSIP configuration, the TSIP is taken out of reset and the DMA enabled.  Errors are immediately reported.  I get frame sync, super frame and error events reported.  The error interrupts report back 0xF1 and 0xF9 errors and seem to be generated in respect to frame sync events.

    0xF1-0xF7 CBA read status (rstatus) errors. (The three least significant bits of this error code are defined in the CBA 3.0 Specification.)

    0xF9-0xFF CBA write status (sstatus) errors. (The three leaast significant bits of this error code are defined in the CBA 3.0 Specification.)

    It is difficult to determine the cause of these errors.  Are these errors a result of some external configuration issue or are they internal errors reported from the device independent of software configuration?

    These are read and write status errors.  Could you please provide the definition of 0xF1 and 0xF9 errors?

    -Steve

  • 0 in reply to Steven Sherbert
    Intellectual 580 points

    Hi Rajarajan U,

    I was able to determine that on the 6678 platform the DMA addresses require to be in GLOBAL ADDRESS space.  The DMA was failing trying to access the memory buffers that were not in that space.

    -Steve