Hello,
I already realized the tutorial: 3.2.2.10. PCIe End Point — Processor SDK Linux for J721e Documentation
It works very well between two J721e on Root complex and Endpoint mode with the ADEX Electronics modified connector.
My second job is to detect a Xilinx FPGA through J721e PCIe link. I currently use an ADT Link connector with the following modified signals:
It doesn't work with the modified cable but if I use the initial cable (without modifiation), my J721e RC can detect the FPGA. I don't want to make a mistake with the power/jtag signals on this cable.
As you can see in the picture, I already removed the clk+, clk- and PERST signals.
My question is: Can you give me the good signals modifications for this cable without power/jtag issues between Jacinto 7 and Xilinx FPGA Please ?
Best regards,
Allan Boileau.