While Bringing up the DDR3 interface I notice the reg_phy_dll_ready bit in the status register is always 0 or toggles intermittently between 0 and 1.
I would like to ask here, what influences the PLL ready status? Is it the jitter in the clock? if so, what is the jitter requirement ?
Is there any way this can be resolved by software?
Hi Joseph,
The purpose of "reg_phy_dll_ready"(DDR PHY Ready) is , it reflects the value on the phy_ready port (active high) that defines whether the DDR PHY is ready for normal operation. The DDR PHY is ready for normal operation, if set to 1.
It refers to "IFRDY" bit DDR3 STATUS register
This has been mentioned in Keystone Architecture DDR3 Memory Controller and KeyStone I DDR3 Initialization (Rev. E) .
This bit "IFRDY" is a interface logic and will be set to '1' only when Levelling completed successfully. Kindly, refer DDR3 Intilaization for levelling (From Page 13).
Thanks,
Rajarajan U
