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TDA4VM: GPIO0 Interrupt

Tao Xie
Intellectual 435 points
Part Number: TDA4VM


Hi，experts

I've been studying how to use GPIO interrupt recently.

I want to change the pin AC4 of GPIO0 to general GPIO and use its interrupt on MCU2_0.

But I see the following link saying:

GPIO0 is allocated to A72

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/972622/tda4vm-tda4-j721e-gpio-interrupt-not-response

Is that true? Does this mean that MCU2_0 or other cores cannot access gpio0?

However, the pins of SPI0 and SPI1 also belong to GPIO0 .

Can only A72 access SPI0 and SPI1?

Best Regards,

Tao

  • 0
    TI__Guru**** 485615 points

    Hi Tao,

    Well, same pin can also be used for GPIO4 (VGPIO_SEL field in pinmux) and GPO4 is allocated for mcu2_0, so you could get the interrupt on mcu2_0 and can use gpio functionality using gpio4. 

    Both the SPIs can be accessed from the mcu2_0.

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 435 points

    Hi，Brijesh

    Thank you very much for your reply.

    According to the figure below, I seem to understand why you said to use the gpio4 pin.

    In tda4vm, gpio0, gpio2, gpio4 and gpio6 are integrated together.

    Then the figure below shows that I can use VGPIO_SEL to switch GPIO.

    But my question is how to modify VGPIO_SEL, and I found 173 CTRLMMR_PADCONFIG. Which one do I need to modify to switch to gpio4?

    Best Regards,

    Tao

  • 0 in reply to Tao Xie
    TI__Guru**** 485615 points

    Hi Tao,

    Tao Xie said:

    But my question is how to modify VGPIO_SEL, and I found 173 CTRLMMR_PADCONFIG. Which one do I need to modify to switch to gpio4?

    This field is available in the pinmux register, so where you are setting pinmux, please update bit4 and bit5 to select GPIO module. Could you tell me which GPIO exactly you are planning to use ?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 435 points

    Hi，Brijesh

    Thank you for your timely reply.

    The pins I want to use are: AC4（GPIO0_127）  AD5（GPIO1_0）

    Best Regards,

    Tao

  • 0 in reply to Tao Xie
    TI__Guru**** 485615 points

    Hi Tao,

    GPIO0_127 is available on CTRLMMR_PADCONFIG128 (0x0011C200) and GPIO1_0 is available on CTRLMMR_PADCONFIG129 (0x0011C204). So can you please select VGPIO_SEL in this offset?

    Regards,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Intellectual 435 points

    Hi，Brijesh

    Thank you very much for your reply.

    I have successfully triggered the interruption of GPIO0_127 and GPIO1_0.

    Then, I have a few things to confirm with you：

    First question: Take pin AC4 as an example. In fact, there is only one physical pin, but it can choose to belong to one of GPIO0, GPIO2, GPIO4 or GPIO6, right?

    Second question: If the answer to the first question is yes, what is the reason for the design of this virtual GPIO?

    Third question: When I use interrupts, I find that not all interrupt numbers can be used. Are there any rules for the selection of interrupt numbers?

    Best Regards,

    Tao

  • +1 in reply to Tao Xie
    TI__Guru**** 485615 points

    Hi Tao,

    Tao Xie said:
    First question: Take pin AC4 as an example. In fact, there is only one physical pin, but it can choose to belong to one of GPIO0, GPIO2, GPIO4 or GPIO6, right?

    Yes, that's correct.

    Tao Xie said:
    Second question: If the answer to the first question is yes, what is the reason for the design of this virtual GPIO?

    Number of pins are limited, compared to number of GPIOs, so they are muxed

    Tao Xie said:
    Third question: When I use interrupts, I find that not all interrupt numbers can be used. Are there any rules for the selection of interrupt numbers?

    Well it depends on the allocation of interrupt for the given core. Please refer to the resource manager tool for increasing. Also please refer to below link, to understand which/how GPIO Interrupt router output is connected different cores.

    https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/interrupt_cfg.html#gpiomux-intrtr0-interrupt-router-output-destinations 

    Regards,

    Brijesh