Most of our boards using the C6457 DSP and Micron MT47H16M16 DDR2 SDRAM works OK with our software diagnostics that make use of the CSL.
However, on one board when it makes a call to CSL_ddr2HwSetup the software locks: It is necessary to 'Halt' from CCS and then the the following dialog box appears:
Trouble Halting Target CPU:
Error 0x00000020/-1202
Error during: Execution,
CPU pipeline is stalled and the CPU is 'not ready'. This means
that the CPU has performed an access which has not
completed, and the CPU is waiting. The target may need to be
reset. The user can choose 'Yes' to force the CPU to be 'ready'.
When this is done, the user will have the ability to examine
the target memory and registers to determine the cause of the
CPU stall. If CPU hang is caused by application and it has been
forced to be 'ready', the CPU should not be run without a reset.
Yes - force CPU ready (might corrupt the code)
Disconnect - disconnect CCS so that it can be reset
Retry - attempt the command again
I'm guessing that the CSL is setting up the DSP DDR2 controller registers and the DSP in turn is attempting to read or write to the DDR2 memory in order to set up the DDR2 SDRAM units internal settings.
If there is a connection fault then would the DSP pipeline stall waiting for a signal from the DDR2?
I would like to access the CSL source code if possible but do not know where to obtain access to it?
Other than using expensive JTAG software in order to take control of the DDR2 controller DSP pins and see what the DDR2 memory is doing is there any other way of testing these failures without having the CSL lock up?
There appears to be no easy way other than JTAG of gaining access to the DDR2 controller DSP pins other than JTAG?
