6457 emif interface to fpga

Please go into that CSL function and report the exact line that the program is stuck (whether it is polling for some status. Our AEMIF expert will comment soon.

 * Setting up configuration parameter using HwSetup */

    status =  CSL_emifaHwSetup(hEmifa, &hwSetup);                  // This is the where the programm stuck.
    if (status != CSL_SOK) {
        printf("EMIFA: Error in HW Setup.\n");          
        printf("Read write operation fails\n");
        return;       
    }
    else {
        printf("EMIFA: Module Hardware setup is successful.\n");
    }

Bye.

Hi,

Sorry about the confusion. I meant going into the actual implementation of the following function:

CSL_emifaHwSetup

Hi.

How do I step in into the function ? .

Once I hit F5 the programm stuck.

Please Advise.

Bye.

Hello,

You need the source file for that function. In case the CSL function implementation are not included in your package, here is the link to the CSL.

http://focus.ti.com/docs/toolsw/folders/print/sprc924.html

Open up the file that contains CSL_emifaHwSetup and set a break point at the 1st line of that function. Then single step.

Regards,

Paul

Hi.

I have added the file  csl_emifaHwSetup.c .

The project compiles, Stepping into the function  CSL_emifaHwSetup(hEmifa, &hwSetup);

Stepping further in csl_emifaHwSetup.c  , The programm stops at line 120

hEmifa->regs->AWCC = (hEmifa->regs->AWCC & mask) |

with an error 7282.CCS_ERR1.zip

Can't Single Step Target Programm.

(Error - 1202 @ 0x0) , See file attached.

Bye.

Attention to any TI member.

This problem not solved yet.

Bye.

Instead of single stepping, can you run the program until it gets stuck then halt it? You should see the PC at the line number where it is stuck. Is it still line 120, and does your emulator give an error still?

Jeff

Hi.

I can break on line 120 on  csl_emifaHwSetup.c

However when I breakpoint on the line 231

printf(

"\tInfo: Async read write \n"); on  Emifa_ReadWrite_example.c

The program do reah this point and thge debuger saya it nis running.

Please Advise.

Hi.

3288.emifa.zip

Attached a screenshot of the breakpoint .

Please Advise.

1423.init_emifa.zipHi.

I need to connect an CPLD to the 32 bit data bus of the emif peripheral.

I have some problem with the EMIFA project .

The programm is compiled and debud , The power to the emif is

enabled Set_PSC_State(PD0, LPSC_EMIF64, PSC_ENABLE); 

the emif async registers are not set .

At this setup the programm is stuck at the line

/* Setting up configuration parameter using HwSetup */
    status =  CSL_emifaHwSetup(hEmifa, &hwSetup);       // programm is stuck here.                
    if (status != CSL_SOK) {
        printf("EMIFA: Error in HW Setup.\n");         
        printf("Read write operation fails\n");
        return;      
    }
    else {
        printf("EMIFA: Module Hardware setup is successful.\n");
    }

    The programm is stuck , I don't get the message   printf("EMIFA: Module Hardware setup is successful.\n");

Setup b.

If i enable the async registers as follows.

/* Configure async EMIF */
     EMIFA_CE2CFG = 0x00240120; /* 8-bit async, 10 cycle read/write strobe */
     EMIFA_CE3CFG = 0x00240120; /* 8-bit async, 10 cycle read/write strobe */
     EMIFA_CE4CFG = 0x00240122; /* 32-bit async, 10 cycle read/write strobe */
     EMIFA_CE5CFG = 0x00240122; /* 32-bit async, 10 cycle read/write strobe */
     EMIFA_BPRIO  = 0x000000FE; /* Enable priority based starvation control */
 
 GEL_TextOut( "EMIFA Initializing...\n" );

At this setup if I try to connect to the board .

I get the following error  Error-1202 @ 0x3c0012c0

( see attaced file).

Please Advise

Ephraim Oved

Hi Ephraim,

Your question about the C6457 can be answered by the C6000 Multicore DSP team. They have a better expertise on the product. Below is the link to their forum

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/default.aspx

Regards,

Juliana

[RandyP ed: The Jun 3 1:28 AM US-CDT post belongs in the C6000 Single Core forum. It was a parallel thread to this thread and has been joined hereto.]

Ephraim,

There is confusing information in some of these posts. You may get better responses if you edit some of your above posts (click the pencil icon in the bottom left of your previous post to edit) to correct spelling ("The program do reah this point and thge debuger saya it nis running." - you know what you meant but I do not know what you meant). I think I know what you mean, but edits could be helpful and more inviting.

In the Jun 3 1:28 AM US-CDT post, you talk about being stuck in some C code in at call to a CSL function for which you have the source, then you talk about some configuration code that looks like it may be a GEL file. What is the relationship between the two cases?

Unless your program requires code to be loaded out of the AEMIF ports, the GEL does not need to initialize these registers. Your C code is trying to initialize these registers when it locks up. It is not clear to me how the un-named "Setup a" and the named "Setup b" are related or what commands are called manually to cause each to occur. Do you understand what I am missing? For technical issues, I tend to need a lot of precision, because my guesses can be wrong and therefore mis-use your time and mine.

What are the values in your *hEmifa and hwSetup structs? Set a breakpoint at the call to CSL_emifaHwSetup, then when you reach the breakpoint open a Watch Window (local may work or not), find or type the two structs, set format to hex, expand the structs as needed, then get a screen capture. You might try the Insert Image icon, or is that how you have been inserting the files already? If you paste the screen capture into MS Paint, you can save as jpg and the file size will be much smaller than bmp, just for your information.

One value that I question is why hwSetup.asyncWait != NULL since you are not using the ARDY input. Please check the state of the ARDY pin and double-check the value for hwSetup.asyncWait.

The FPGA/CPLD may be causing problems on the emif bus or the connector. This is not a common problem but should be verified by running all of these commands and programs without the fpga connected to see if the results are different. That will help very much in narrowing down your cause, especially because the code should not be locking up where it does.

ephraim oved said:

I get the following error  Error-1202 @ 0x3c0012c0

This error seems to be saying that the DSP or emulator is trying to read from the L3 ROM and is failing. This is unusual, so I still suspect hardware issues because of the FPGA. If not, this will have to be studied some more or worked around.

ephraim oved said:

status =  CSL_emifaHwSetup(hEmifa, &hwSetup);       // programm is stuck here.

In your earlier posts, you mentioned that you are debugging into the CSL_emifaHwSetup function, and that you have included the C source for this function to allow you to do that. In one picture (emifa.bmp), you had a breakpoint at line 120 in csl_emifaHwSetup.c. Next time you run to there, check all the values that are about to be accessed; most are in the hwSetup struct, then one is the AWCC register. Bad pointers have a way of causing problems in code, too, but that would happen regardless of the hardware issues, so you have two different paths to take in your debugging before we get back together in a couple of days.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

Hi Randy.

I am sorry for the confusing information , I will try to make myself clear as possible.

I intend to attach a CPLD to the emif bus , Currently the emif connecotr is not connected to any hardware.

All I need at this moment all I need is to see that the emif is active .

Now for the test , I followed your advise and I breakpoint on the line

 status =  CSL_emifaHwSetup(hEmifa, &hwSetup);

I can see that something with the structure is wrong .

Please Advise.

Thanks.

Ephraim,

I hope you are willing to laugh at my bad advice. I have seen many pictures inserted into posts that allowed me to expand it enough to see the numbers and text, but this one is not clear enough. I expanded it a lot in FireFox, but the blurs got larger. I do not know if the problem is with using .jpg instead of .bmp, or with inserting an image instead of attaching it, or just the fact that I wear trifocal lens glasses. But I cannot read enough of your Watch (2) window to guess what data are in the structs.

If you are willing to help me understand the problem with the image, please do me this favor in your next post. Please use the convenient you used above to include the .bmp version of the file, and also do the previous method to include a zip file with both the .bmp and .jpg versions. I apologize for the bad advice, but I will be much smarter about this if you can do these for me.

Please open more of the embedded structs, too, please. You can click on the + signs a bit deeper to get more information in the Watch (2) window.

ephraim oved said:

I can see that something with the structure is wrong .

This is good news. And the fact that your CPLD is not yet connected eliminates a lot of the debug direction I was considering before. And it shows that you and I are alike in trying to take one step at a time.

Since you see something wrong with one of the structs (I assume hwSetup since you have it highlighted in the source window, but I am guessing still), you can look back through your code to see when the wrong field values were written and determine why or what needs to be done differently.

Regards,
RandyP

Hi.

I am not laughing at all , I just want this nighmare over .

Attached 2 jpg screenshots .

The left notification pops up as I expand the hEmifa regs.

See that the regs type in unknown , I don't understand what it means.

The same "unknown structure" happens with the hwsetup structure.

Please Advise.

Ephraim Oved.

Whatever you did differently worked well for the jpg's. I was able to expand them large enough to read this time. Thank you.

For the first picture, showing hEmifa, this is troubling that you cannot read from 0x70000000. Please try directly reading it at different points in your debug flow, such as immediately after connecting and/or reset, after loading and running to main(), even at the same point in your program. Try reading by either using another watch window on *(int *)0x70000000 or a small memory window at that address.

For the second picture, showing hwSetup, ceCfg[1] and [3] are NULL, which I doubt is what you intended. Please look at where you set the values in hwSetup and make any corrections needed. At the least, you can set asyncWait = NULL since you are not using ARDY; this will change the location of the failure, but will probably not get rid of it.

Whatever is causing you to be unable to read from 0x70000000 is what will likely turn out to be the problem here. But that could be an initialization problem related to powering up and clocking the EMIFA peripheral. Please double-check what you have done there, and try to find a working example from the support examples.

I know this is not a lot of help, yet, but you are making progress toward finding the problem.

Regards,
RandyP

Looks like there is a problem with how "regs" is getting allocated. Address 0x70000000 is not a valid memory location in the memory map. That should be in either the internal or external memory. Step through the code where that gets allocated and see if anything fishy is going on, or if it is getting overwritten later.

Jeff

Jeff,

My copy of the C6457 datasheet says that the EMIFA Configuration Registers are at 0x70000000. Is there a 0 missing in the example above, or is the datasheet wrong?

Respectfully,
RandyP

Sorry I must by dyslexic. I thought the part number was C6745, so disregard my comment.

Jeff

Hi, Ephraim!

There is two switch panels on your evaluation board: SW3 and SW4. Try switching 7th switch of SW3 panel to ON. Hopefully, that would solve your current problem.

... But it seems, that you would also run into another, as I just did: my EMIFA is simply not functioning, and CE2 pin would not go from HIGH to LOW state to begin access interval. :(

UPD: Oh, I see on other forum thread, that you have found this already and hopefully working now with EMIF. Could you please post your EMIF initialization sequence (including PLL part and perhaps something else that needs to be done) for this board? Examples in CSL seem not to work...

UPD!!!

Just in case anyone would stuck as I did, there are several resistors (R184, R177, R170, R160, R165, R155, R200 and perhaps R210) on this TMDSEVM6457L board that are "NU" (not used). One has to solder them on the board in order to use EMIF.

F***  Mein Gott! Why the documenting in TI has always been so poor... "User Guide" should have had that mentioned.