[EDIT] I found some new information and wrote a new post after this one with different conclusions, please consider both of them before providing a reply[/EDIT]
Hello everybody,
I'm working on a TMS20C6455 DSK board and I'm trying to learn how to configure its working frequencies.
I wrote this simple code in order to get the configuration of the PLL module right after the startup of the board:
[START CODE]
#include <stdio.h>
#include <csl_pllc.h>
void main(void)
{
CSL_Status status;
CSL_PllcObj pllcObj;
CSL_PllcHandle hPllc;
//CSL_PllcHwSetup hwSetup;
CSL_PllcHwSetup hwSetupRead;
status = CSL_pllcInit(NULL);
if(status != CSL_SOK)
{
printf("Errore nell'inizializzazione di PLL1");
return;
}
hPllc = CSL_pllcOpen(&pllcObj, CSL_PLLC_1, NULL, &status);
if((status != CSL_SOK) || (hPllc == NULL))
{
printf("Errore nell'apertura dell'istanza di PLL1");
return;
}
status = CSL_pllcGetHwSetup(hPllc, &hwSetupRead);
printf("La configurazione di default di PPL1 è:\n");
printf("Maschera di abilitazione dei divisori: %x\n", hwSetupRead.divEnable);
printf("Valore del predivisore: %x\n", hwSetupRead.preDiv);
printf("Valore del divisore D4: %x\n", hwSetupRead.pllDiv4);
printf("Valore del divisore D5: %x\n", hwSetupRead.pllDiv5);
printf("Valore del moltiplicatore: %x\n", hwSetupRead.pllM);
printf("Modalità di funzionamento: %x\n", hwSetupRead.pllMode);
}
[END CODE]
I assume that, when reading the setup of the PLL module, I get the content of the configuration registers, which I print to the output window in hex format.
The values are:
divEnable = d (it means PREDIV, D4 and D5 are enabled)
preDiv = 1 (it means it divides the CLKIN1 signal by 2)
pllDiv4 = 8 (should be a reserved value; if could mean the value needs to be defined?)
pllDiv5 = 4 (it means it divides by 5)
pllM = 18 (it means it multiplies by 25)
pllMode = 1 (it means the PLL is configured to work in PLL mode- PLL is not bypassed)
Again, I assume these are the values in the proper register fields, hence their interpretation according to the sprs276k documentation.
So, my questions are: Is the interpretation of these values correct? The code I wrote provides them in a correct shape? If so, why is D4 set with a reserved value?
Moreover, the board documentation states the default working frequency is 1000 MHz, but given the values I get and with a CLKIN1 signal at 50 MHz, it comes out:
[50/(PREDIV=2)]*(MULT=25)=625 MHz
Is there something I'm missing or that's quite an inconsistency?
Hope you can help me to clarify my doubts.
Regards,
Francesco Annese
