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Switch from OMAP35 to DM37: L2 initialization problem

Other Parts Discussed in Thread: OMAP3530, DM3730

Hello everybody,

we had our own OMAP35x board and adapted it to DM37x. Now the system seems to reset on the L2 cache initialization:

      mov     r12,#0x1
      smc     #0x0

OMAP35x is working on the same board. Since there should not be any changes in L2 between both processors, I'm looking for a reason for this crash.


Any idea is appreciated!

Thank you and best regards, Philipp.

  • Philipp,

    Do you have debug capabilities? Are you getting an undefined instruction?

    Can you verify if the Cortex-A8 is not in "user" mode.  That would cause an undefined instruction (see excerpt below)

     

    You can check the mode bits of the CPSR register. For example user mode would be Mode[4:0] = 0x10.

    === From the Cortex-A8 -r3p2 Technical Reference Manual =====

    2.15.9 Software Monitor Instruction

    When the processor executes the Secure Monitor Call (SMC) instruction, the core enters

    Monitor mode to request a Monitor function.

    Note

    An attempt by a User process to execute an SMC causes an Undefined Instruction

    exception.

     

    ========

  • Hello Jeff,

    thank you for your answer. Yes, I'm accessing the core via JTAG (Lauterbach debugger).

    At this point of startup, we are in svc mode (0x13), which should be okay.

    I don't expect this to be a Cortex-A8 related issue, because it runs on OMAP35x.

    Any other ideas of what to test?

    Thank you and regards, Philipp.

  • A related detail is that the ROM code disables L2 cache on the DM3730 prior to branching to your code (it did not do that on OMAP3530).  I don't see exactly how that ties into your problem, though I imagine it might be related.

  • Can you also check whether your device is GP device or not? I remember, during one of bringup I had similar issues (I don't remember exact instruction and place), but that was due to non GP device.

    Look at CONTROL_PRODUCTION_ID register.

    Thanks,

    Vaibhav

  • Can you read the PC address after the smc instruction.  Is it vectoring to the right location? I was reading that you have to set up the Interrupt vector table location separately for the secure monitor.

  • Ensure you are following the correct sequence out of the Cortex-A8 TRM to enable L2 cache.  Note some of the instructions below require the SMI instruction on OMAP35x/AM37x.  Also ensure MMU is disabled when you try this.

    From Cortex TRM... 
     To enable the L2 cache following a reset or to change the settings of the L2 Cache
    Auxiliary Control Register, you must use the following sequence:
    1. Complete the processor reset sequence or disable the L2 cache.
    2. Program the L2 Cache Auxiliary Control Register. See c9, L2 Cache Auxiliary
    ;Control Register on page 3-124 for details.
    Note
    If you have configured the processor to support parity or ECC memory, you must
    enable those features before you can program the C bit.
    3. Program the Auxiliary Control Register to set the L2EN bit to 1. See c1, Auxiliary
    Control Register on page 3-61 for details.
    4. Program the C bit in the CP15 Control Register c1. See c1, Control Register on
    page 3-58 for details.

    Regards,

    James

  • Hell Vaibhav,


    the register contains 0160 7164 0A02 B014 CAFE B891 0000 00F0, which doesn't completely match the description in the TRM. There is an F0 for "GP", but at the wrong position. But as the silicon type is also at a different position, I guess it's an error in the TRM.

     

    Thanks, Philipp.

  • Hello Jeff,

    > Can you read the PC address after the smc instruction.

    I don't know how to! The debugger can't single-step a device reset, so the machine is running somewhere in the boot ROM when I stop it. I tried setting break points at 0x14000ff, but it seems the reset takes the PC somewhere else. If you know how I can identify the position where the reset takes me, I'll tell you.

    Thanks, Philipp.