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DRA829J: GPMC "DMA mode is not supported"

Part Number: DRA829J
Other Parts Discussed in Thread: AM5749, TDA4VM, , AM6526

Hello TI Experts,

Previously, using the AM5749 processor, we had successfully implemented a parallel interface between a C66x DSP core and an external FPGA using the GPMC peripheral and using DMA to move data between the C66x and GPMC. The performance boost using DMA helped us to meet our throughput requirements.

We have been evaluating whether to move from the AM57x to the Jacinto 7 DRA829J or TDA4VM processors, which also have 2x C66x DSP cores and a newer C7x DSP core, as well as 64-bit Arm.

In the DRA829J and TDA4VM TRM, section for GPMC, it says "DMA mode is not supported". It looks like only GPMC interrupts can be used in this family and DMA is not connected to the GPMC.

Is there a way to achieve similar performance to the AM57x GPMC with DMA, but without using DMA for the DRA829J/TDA4VM?

Or will the performance inevitably decrease, since the DMA is no longer connected? I'm hoping there was a good solution, when it was decided to remove the DMA from the GPMC.

In a similar post for the AM6526, which also says "DMA mode is not supported" in the TRM, it's stated that DMA transfers can still be used to move data to/from GPMC space, but it must be initiated and monitored by a CPU. This means we'd probably need to use one of the other cores to initiate and monitor DMA transfers to/from GPMC if we want to minimize overhead for the C66x core? The C66x core will be continuously reading data acquired from the GPMC-FPGA link, processing the data, and then writing new data to the GPMC-FPGA link.

Does this also apply for DRA829J/TDA4VM?

Just wondering what the best way to maximize the GPMC performance would be if there's no DMA.



  • Steve,

    The DMA Mode refers to a mode where an internal Fifo triggers events to a DMA.  That DMA Event is not hooked up at SoC level.

    You can still use DMA to read/write to memory/peripheral that is interfaced to the GPMC on your PCB.