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Regarding EDMA3 usage in DM814x

Radhesh Bhat
Genius 4590 points

Hi ,

Currently i am using C67x DSP for my algorithm along with EDMA3. In my algorithm there are two types of transfer, one is from DDR to L2 RAM and other is L2 RAM to DDR.

So for these transfers i am using EDMA3. What i am observing is that for the first trigger (DDR -> L2) , transfer is not happening. And for the other trigger (L2 -> DDR), all zeros are transferred though the source content is proper. I guess there is a cache issue (if its really) which i am unable to figure how to tackle. 

The base of address of L2 RAM is 0x10800000 viewed from DSP.

Other observation is that in CCS memory window, it shows tick mark enabled for L1D and L2 cache. Is there any way to disable the L2 cache and use it as a RAM. I was bit confused by the documentation in the TRM. Can some one please help in this regard?

Regards
Radhesh 

 

 

  • 0
    Genius 4590 points

    HI,

    Is there a protection for L2 because of which EDMA3 is not able to access the L2 RAM (i looked into Memory Protection Page Attribute Register for L2 and all the bits for IDs are enabled meaning access permissions are available for all IDs). Basically i tried simple test application for EDMA3. DDR->DDR is working fine. But DDR->L2 , there is no change the L2 destination. L2->DDR, the DDR content becomes zero with amount of data programmed by ACNT and BCNT.

    Looking forward to help from the community.

     

    Regards

    Radhesh

     

  • 0 in reply to Radhesh Bhat
    Genius 4590 points

    Finally I was able to make EDMA3 work with DDR <-> L2 transfers in Centaurus. EDMA3 memory map is same as L3 memory map, so EDMA3 sees L2 RAM of DSP as 0x4080_0000. After this change, my application started working. Thanks.

     

    Regards

    Radhesh

  • 0 in reply to Radhesh Bhat
    Expert 2030 points

    Where should this change be made? Which source file? 

    I am having the same issue with TI8168 DSP DMA using ACPY3/DMAN3, I am not seeing DDR3 <-> L2 transfer or L2 <-->DDR3.

    But  DDR3<->DDDR3 works fine.

     

    RV


  • 0 in reply to RV
    Genius 4590 points

    RV,

    I have not used any DMAN3/ACPY3 APIs for EDMA programming, i have a standalone app where i directly program the EDMA param address space and registers. 

    The physical address of DSP L2 is 0x4080 0000 (L3 memory map), so try with 0x4080 0000 for your EDMA programming when you include DSP L2 either as source or destination  as EDMA can see only L3 memory map.

     

    Hope this helps.

     

    ~R