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THS8200 output 720P VGA

Other Parts Discussed in Thread: THS8200

I  am use DM365 +THS8200 + THS 7303 output 1280X720 VGA signal to Computer Monitor, but I found there are Sync signal inserter on G (green) channel .

I want to know how to program   THS8200  in the RGB output without Sync signal  insertion/General-Purpose Application DAC?

this is my THS8200 setting :


  printk("ths8200 set THS8200_720P_60\n ");
  WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl  frequency range=high

  //YCbR to RGB         
  WR_REG,THS8200,0x01,0x04,0x81 // csc_ric1           
  WR_REG,THS8200,0x01,0x05,0xD5 // csc_rfc1           
  WR_REG,THS8200,0x01,0x06,0x00 // csc_ric2           
  WR_REG,THS8200,0x01,0x07,0x00 // csc_rfc2           
  WR_REG,THS8200,0x01,0x08,0x06 // csc_ric3           
  WR_REG,THS8200,0x01,0x09,0x29 // csc_rfc3           
  WR_REG,THS8200,0x01,0x0A,0x04 // csc_gic1           
  WR_REG,THS8200,0x01,0x0B,0x00 // csc_gfc1           
  WR_REG,THS8200,0x01,0x0C,0x04 // csc_gic2           
  WR_REG,THS8200,0x01,0x0D,0x00 // csc_gfc2           
  WR_REG,THS8200,0x01,0x0E,0x04 // csc_gic3           
  WR_REG,THS8200,0x01,0x0F,0x00 // csc_gfc3           
  WR_REG,THS8200,0x01,0x10,0x80 // csc_bic1           
  WR_REG,THS8200,0x01,0x11,0xBB // csc_bfc1           
  WR_REG,THS8200,0x01,0x12,0x07 // csc_bic2           
  WR_REG,THS8200,0x01,0x13,0x42 // csc_bfc2           
  WR_REG,THS8200,0x01,0x14,0x00 // csc_bic3           
  WR_REG,THS8200,0x01,0x15,0x00 // csc_bfc3           
  WR_REG,THS8200,0x01,0x16,0x14 // csc_offset1        
  WR_REG,THS8200,0x01,0x17,0xAE // csc_offset12       
  WR_REG,THS8200,0x01,0x18,0x8B // csc_offset23       
  WR_REG,THS8200,0x01,0x19,0x15 // csc_offset3  

  WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl  20bit 422

  WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
  WR_REG,THS8200,0x01,0x1E,0x00 // dtg_y_sync2        
  WR_REG,THS8200,0x01,0x1F,0x00 // dtg_y_sync3        
  WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
  WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
  WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
  WR_REG,THS8200,0x01,0x23,0x2A // dtg_y_sync_upper   
  WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper
  
  WR_REG,THS8200,0x01,0x34,0x06 // dtg_total_pixel_msb adjust for various graphics formats
  WR_REG,THS8200,0x01,0x35,0x72 // dtg_total_pixel_lsb
  WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb    
  WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb    


  WR_REG,THS8200,0x01,0x38,0x87 // dtg_mode     VESA Slave       


  WR_REG,THS8200,0x01,0x39,0x27 // dtg_frame_field_msb  adjust for various graphics formats
  WR_REG,THS8200,0x01,0x3A,0xEE // dtg_frame_size_lsb 
  WR_REG,THS8200,0x01,0x3B,0xFF // dtg_field_size_lsb 
  //CSM setup to map YCbCr to FS RGB        
  WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
  WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
  WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
  WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
  WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high  
  WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high  
  WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
  WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
  WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
  WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
  WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
  WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
  WR_REG,THS8200,0x01,0x4D,0xAC // csm_mult_bcb_lsb   
  WR_REG,THS8200,0x01,0x4E,0xAC // csm_mult_rcr_lsb   
  WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode   
         
  WR_REG,THS8200,0x01,0x70,0x28 // dtg_hlength_lsb    adjust HSOUT width for various formats
  WR_REG,THS8200,0x01,0x71,0x01 // dtg_hdly_msb       
  WR_REG,THS8200,0x01,0x72,0x4 // dtg_hdly_lsb       
  WR_REG,THS8200,0x01,0x73,0x05 // dtg_vlength_lsb     adjust VSOUT width for various formats
  WR_REG,THS8200,0x01,0x74,0x02 // dtg_vdly_msb       
  WR_REG,THS8200,0x01,0x75,0xED // dtg_vdly_lsb       
  WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
  WR_REG,THS8200,0x01,0x77,0x07 // dtg_vdly2_msb      
  WR_REG,THS8200,0x01,0x78,0xFF // dtg_vdly2_lsb      
  WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb   adjust for horizontal alignment
  WR_REG,THS8200,0x01,0x7A,0x0A // dtg_hs_in_dly_lsb  
  WR_REG,THS8200,0x01,0x79,0x00 // dtg_hs_in_dly_msb   adjust for horizontal alignment
  WR_REG,THS8200,0x01,0x7A,0x32 // dtg_hs_in_dly_lsb  
  WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb   adjust for vertical alignment
  WR_REG,THS8200,0x01,0x7C,0x00 // dtg_vs_in_dly_lsb  
  WR_REG,THS8200,0x01,0x82,0x5B // pol_cntl   HS/VSin ++, HS/VSout++, FID - 


  WR_REG,THS8200,0x01,0x03,0x00
  mdelay(50);
  WR_REG,THS8200,0x01,0x03,0x01

I want to know how to program   THS8200  in the RGB output without Sync signal  insertion/General-Purpose Application DAC?

please help me!

  • Hello,have you resolve this problem "program   THS8200  in the RGB output without Sync signal  insertion/General-Purpose Application DAC?"

    Now, I have met this problem. If you have resolved it ,please help me, thank you .

    My E-mail address is woshizhouhaijun@163.com

  • Hello :

          Have you resolved this problem ? We met the same problem, if you got a solution, would you please let me know what to do?

                                                                                                                                          Thank you ,my email: pop007755@163.com