TDA4VM: The Samsung emmc can't be identified on HS200 mode

Ruifeng Zhang

Part Number: TDA4VM

Hi Shiou Mei,

Continue the previous thread: TDA4VM: The Samsung emmc can't be identified on HS200 mode - Processors forum - Processors - TI E2E support forums,

1.The first problem is emmc can not found .

When trying to grab the waveform again, the problem cannot be reproduced. It can be reproduced when the oscilloscope probe is not connected and cannot be reproduced when the probe is connected.
The probe: we use the differential probe and the signal-ended probe
Is there any way to solve it?

2.The second problem is about the emmc test.

Read data from emmc:
The clk have the 22R series resistance between the SOC and emmc,and the data have 33R.
Test the emmc in 200MHz.we found the setup time less than 1.4ns,does not meet the requirements.
Change the 22R to 0R in clk,we found the setup time can meet the requirements.
Can change the delay or IO drive in somewhere?

Read the data is fail if CMD connect the probe, is there any other way to solve it?

Write data to emmc:
The clk have the 22R series resistance between the SOC and emmc,and the data have 33R.
Test the emmc in 200MHz.Write the data is fail if DATA or CMD connect the probe, is there any other way to solve it?

Thanks!

over 3 years ago

0 Ruifeng Zhang over 3 years ago

Intellectual 570 points

Hi Shiou Mei,

Could you help to give some suggestions ?

0 Shiou Mei Huang over 3 years ago

TI__Genius 10180 points

Ruifeng,

I have received your question. Will take a look into the latest information you provided and reply back with additional comments/ questions.

Best Regards,

Shiou Mei

0 Shiou Mei Huang over 3 years ago in reply to Shiou Mei Huang

TI__Genius 10180 points

Ruifeng,

A few questions:

Where is the 22R series resistance connected? A series termination resistor is typically used to avoid reflection and improve signal integrity; it sounds like in your case the signal integrity is actually better without the termination resistor, is this correct?

Moreover, in HS200 mode, TDA4VM dynamically tunes the CLK used for data capturing so the data will be captured with good setup/hold margin. As a result timing requirements are not defined for this particular mode in our datasheet. Where did you read 1.4 ns as the setup requirement?

As for the first issue related to eMMC not found, it sounds like the probe loading may be affecting the signals. Can you describe in more detail what the eMMC issue is?

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi TI:

We want to solve the Samsung emmc can not be identified on HS200 mode as soon as possible.(That can be identified on other mode. )

If we add 10pF in CMD line that the emmc can be identified on HS200 mode.

We think that EMMC AC or Timing TEST problem can be related to it.

The system start ,we can find the CMD6 error in log after mount emmc.

We use the oscilloscope to test CLK and CMD line, the CMD6 is successed in log after mount emmc.

We think the parasitic parameters of probe affect the phase of CLK and CMD . （We try to use the differential probe and the signal-ended probe）

We asked EMMC manufacturers to analyze.

They found that the waveform phase of CLK before and after the discontinuity changed nearly 180 degrees from that of CMD.

This is against the EMMC specification.

Previously, you wanted us to measure the waveform and data of the CMD6 error, because the probe will affect the identification of the EMMC. We have not been able to successfully measure the waveform you want.

Do you have some other methods over there？

Based on the above, please give me some suggestions for modification？

Thanks!!

0 Shiou Mei Huang over 3 years ago in reply to guo kuo

TI__Genius 10180 points

Guo,

All devices start with backwards-compatible timing. In this speed mode, CMD and DAT are all sampled on the rising CLK edge, but the signals can be launched off of falling CLK edge. While in HS200 mode, CMD and DAT are both sampled and launched off of rising CLK edge. CMD6 is the command used to switch the modes, so that would explain why you saw a phase change after the CMD launches.

Yes, the probe loading indeed may be affecting CLK-DAT signals. Are you using active probes with low capacitance for the measurements? Please share the waveform you measured, even if the system is passing during the measurement as well. Also note the location of the measurement. If failure is a read, probe closer to the TI processor. If failure is a write, probe closer to the Samsung eMMC device.

In previous comments a 22R series resistance on the CLK lane and a 33R on DAT lane was mentioned. Where are these resistors located? Can you replace these resistors with 0 ohms and probe the waveform to understand the effects they have on your system?

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi TI:

Here are some questions to ask you.

1.In backwards-compatible timing mode we found the CMD is sampled on the falling CLK edge, but the signals can be launched off of rising CLK edge .

The clk is 400KHz not 200MHz, is right?

2.I would like to confirm with you, is the conversion of HS200 mode in TI's driver according to the following process?

3.How to understand “ While in HS200 mode, CMD and DAT are both sampled and launched off of rising CLK edge. ”？

I think CLK input parameters should be measured while CMD and DAT lines are stable high or low, as close as possible to the Device.

If CMD and DAT are both sampled and launched off of rising CLK edge，is the collected data unstable?

For the series resistance problem，we will conduct some tests according to various states and provide feedback later.

Thanks！！

0 Shiou Mei Huang over 3 years ago in reply to guo kuo

TI__Genius 10180 points

Guo,

1. Yes, during initialization the clock is only running at 400 kHz. It does look like in your capture the DAT/CMD is launched off of the rising edge clock instead of the falling edge CLK.

a. When are you capturing the waveform?

b. Was device already switched into HS200 mode but the frequency hasn't been updated to 200 MHz (Step 4 of the sequence you pasted)?

c. What values do you have set in MMCSD0_SS_PHY_CTRL_4_REG and MMCSD0_SS_PHY_CTRL_5_REG?

d. A while back we were looking into the setting of MMCSD0_HOST_CONTROL1[2] HIGH_SPEED_ENA. Can you check if this bit is getting set?

Please also confirm if the waveform is TI output, or eMMC output.

2. The sequence you shared looks correct

3. Agreed with you CLK capture should happen when CMD and DAT are stable. In HS200 mode, the standard procedure is for host/device to drive CMD/DAT off rising edge CLK such that the signal will be stable before the rising edge CLK capture.

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

> a. When are you capturing the waveform?

We measure the waveform at the CMD6 return error.

> b. Was device already switched into HS200 mode but the frequency hasn't been updated to 200 MHz (Step 4 of the sequence you pasted)?

The device should be in LS mode and prepare to switch to HS200 when send CMD6 to set bit width error.

> c. What values do you have set in MMCSD0_SS_PHY_CTRL_4_REG and MMCSD0_SS_PHY_CTRL_5_REG?

In this time, the MMCSD0_SS_PHY_CTRL_4_REG & MMCSD0_SS_PHY_CTRL_5_REG was set to 0x10610f & 0x7. And the HIGH_SPEED_EN was not be set.

> d. A while back we were looking into the setting of MMCSD0_HOST_CONTROL1[2] HIGH_SPEED_ENA. Can you check if this bit is getting set?

Please also confirm if the waveform is TI output, or eMMC output.

As discussed earlier, the MMCSD0_HOST_CONTROL1[2] HIGH_SPEED_ENA flag does not need to be set before switching to HS200 mode.

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi:

a.The waveforms captured before and after clk stutter.

Before the clk stutter：

Clk stutter：

After clk stutter：

Please also confirm if the waveform is TI output, or eMMC output.

We think the waveform is TI output.

We can see that the first two bits of the waveform are “01” at two cycle.That is host output in EMMC specification.

Can i understand CMD and DAT are both sampled of rising CLK edge？

That is to say, CMD and DAT are in a stable state on the rising edge of CLK and should not be in a transition state.

So in the case where the CMD measured in the above figure jumps on the rising edge of CLK, is there a problem?

Thanks！！

0 Shiou Mei Huang over 3 years ago in reply to guo kuo

TI__Genius 10180 points

Guo, Ruifeng,

Yes, CMD and DAT should be stabilized around the capturing CLK edge. MMCSD0_SS_PHY_CTRL_4_REG and MMCSD0_SS_PHY_CTRL_5_REG are used to control the delay between CLK and CMD/ DAT, and should be set accordingly based on the speed mode. In Legacy Speed Mode, PHY_CTRL5_REG [17:16] SELDLYTXCLK and SELDLYRXCLK should be set to 0x1.

Are you seeing write or read issues?

The host gates the CLK when no active CMD or DAT are being transmitted, that's why there is a break in-between continuous CLK transmission. It appears before/after the gated CLK, the MMCSD0_HOST_CONTROL1[2] HIGH_SPEED_ENA bit was set by SW. Can you read out the entire bits sent on the CMD lines for two CMDs before and after the gated CLK section? Please include both the data transmitted by the host as well as the eMMC device.

Based on the waveform you shared, should be in this format:

(2 CMD Prior) ?

(1 CMD Prior) 0 1 001101

Gated CLK

(1 CMD After) 0 1 000110

(2 CMD After) ?

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi:

Based on the waveform:

Before gated CLK:

If sampling by rising edge，CMD is 0 1 001101.

Gated CLK:

After gated CLK:

If sampling by falling edge，CMD is 0 1 000110.

For the series resistance problem：

There is a 22R series resistance on CLK placed close to the SOC side.

There is a 33R series resistance on CMD placed close to the EMMC side.

There is a 33R series resistance on DATA placed close to the EMMC side.

We try to adjust either on CLK/CMD to 0R，then EMMC can be recognized in HS200 mode.

But when we conduct the EMMC read and write test, once the CMD is connected to the probe, the frequency will immediately drop to 400KHz, and an error will be reported on the log.

We think that the adjustment of this series resistance is the same as adding a capacitor to the CMD.

Whether adjusting the delay or drive capability can solve this problem.

Thanks！！

0 Shiou Mei Huang over 3 years ago in reply to guo kuo

TI__Genius 10180 points

Guo,

Please read out the complete 48-bits CMD and corresponding response from the eMMC.

Glad to hear HS200 worked after removing the series resistor! Our reference design doesn't recommend placing a resistor in between the SoC-eMMC path unless it helps improve your signal integrity. Are you seeing better signal integrity after the resistors are added?

Moreover, make sure you are using active probes with low capacitance and short fly-wires to measure the signals; this will help minimize the probe's affect. If you power on the board with the probes attached, do you see the same issue as before?

eMMC drive strength can be set in MMCSD0_SS_PHY_CTRL_1_REG; more information can be found in the TRM.

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi：

First make sure the waveform problem：

Regarding the waveforms of CLK and CMD phases we tested at 400KHZ, combined with TI's drive, do you think there is a problem?

If there is no problem and it meets TI's requirements, why not focus on this waveform?

If there are problems and do not meet TI's requirements, what direction should be improved?

Second about the EMMC AC timing problem：

There are time requirements in HS200 mode in the EMMC specification.

As you provide“Moreover, in HS200 mode, TDA4VM dynamically tunes the CLK used for data capturing so the data will be captured with good setup/hold margin. As a result timing requirements are not defined for this particular mode in our datasheet. Where did you read 1.4 ns as the setup requirement? ”

So, do we still need to test according to the EMMC standard, including some parameters such as setup time and hold time？

Or TI's driver will automatically adjust this time, we don't need to pay attention？

The third question about series resistance：

We have tried mounting the probe before testing, and mounting the probe during testing.The result is that an error will be reported in the log, and the frequency will become 400KHz.

In terms of probes, active differential probes have been used for testing, and the effect is the same. (This probe can be used to test signals such as MIPI/SGMII/PCIE).

Since the probe has such a great influence on the CMD, does it mean that the phase margin of the CLK/CMD is not good enough?

Thanks！！

0 Ruifeng Zhang over 3 years ago in reply to guo kuo

Intellectual 570 points

Hi Shiou Mei,

> MMCSD0_SS_PHY_CTRL_4_REG and MMCSD0_SS_PHY_CTRL_5_REG are used to control the delay between CLK and CMD/ DAT, and should be set accordingly based on the speed mode.

According to TRM, I have learned that modifying OTAPDLYENA and OTAPDLYSEL can control the delay of CLK TX. Is it right ? Can you give me a suggested value?

> eMMC drive strength can be set in MMCSD0_SS_PHY_CTRL_1_REG; more information can be found in the TRM.

Please help clarify which bit field of the MMCSD0_SS_PHY_CTRL_1_REG register need to be changed to improve the strength of the EMMC driver?

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Guo, Ruifeng,

Q: Regarding the waveforms of CLK and CMD phases we tested at 400KHZ, combined with TI's drive, do you think there is a problem?A: The waveform shows the DAT is launched off of rising CLK edge. Data should be launching off of falling CLK edge in Legacy Speed Mode (400 kHz) unless it is already changed into HS200 mode by CMD6, in which case, OTAPDLYSEL ratios should be set accordingly.

Can you print out the register value for MMCSD0_HOST_CONTROL1 throughout the dump log that also shows where failure happened? Moreover, it was requested earlier to print out complete 48-bits CMD and corresponding response from the eMMC. Please provide this information as well.

(2 CMD Prior) 0 1 001101 and ?

(1 CMD Prior) 0 1 001101 and ?

Gated CLK

(1 CMD After) 0 1 000110 and ?

(2 CMD After) 0 1 000110 and ?

Q: So, do we still need to test according to the EMMC standard, including some parameters such as setup time and hold time? Or TI's driver will automatically adjust this time, we don't need to pay attention？
A: Tuning algorithm is only applicable for HS200 mode when read by the host according to eMMC standard. Setup/hold time still needs to be checked for lower speed mode like Legacy SDR, High Speed SDR, High Speed DDR, and for input into the eMMC device.

Q: Since the probe has such a great influence on the CMD, does it mean that the phase margin of the CLK/CMD is not good enough?
A: Since the device is the one not able to read proper CMD, please make sure you are probing on the eMMC side. If this waveform is probed on eMMC side, then you can check eMMC spec to confirm if the CLK/CMD phase meets setup/hold time requirements. Setup/hold time can be affected by series termination resistor, impedance mismatch, etc.

Q: According to TRM, I have learned that modifying OTAPDLYENA and OTAPDLYSEL can control the delay of CLK TX. Is it right ? Can you give me a suggested value?
A: The value can be found in the data manual.

Q: Please help clarify which bit field of the MMCSD0_SS_PHY_CTRL_1_REG register need to be changed to improve the strength of the EMMC driver?
A: Bits [22:20] DR_TY changes the host's drive strength.

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

Hi ShiouMei,

> Q: According to TRM, I have learned that modifying OTAPDLYENA and OTAPDLYSEL can control the delay of CLK TX. Is it right ? Can you give me a suggested value?
> A: The value can be found in the data manual.

According to the Table 12-6154. MMCSD0_SS_PHY_CTRL_4_REG Register Field Descriptions in TRM, the ITAPDLYENA and ITAPDLYSEL is using for the non-HS200/HS400 mode. Why is it suggested to be set in data sheet tda4vm.pdf ?

0 Ruifeng Zhang over 3 years ago in reply to Ruifeng Zhang

Intellectual 570 points

Hi ShiouMei,

> Can you print out the register value for MMCSD0_HOST_CONTROL1 throughout the dump log that also shows where failure happened? Moreover, it was requested earlier to print out complete 48-bits CMD and corresponding response from the eMMC. Please provide this information as well.

The registers dump log is:

Fullscreen emmc log failed.txt Download

Ruifeng Begin to set HS200...
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x0 SDMMC_SS_PHY_CTRL5(0x110) = 0x0
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x1157e74000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng End to set HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x0 SDMMC_SS_PHY_CTRL5(0x110) = 0x0
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x1157e74000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b7 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
Unable [0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
to acc[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
ess /dev/emmc0t179
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x1157e74000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b7 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
Mounting the sd ..
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x800, blks 8, blksz 512, timeout 10000ms
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

The emmc can be recognize when changed the series resistor, the log is:

Fullscreen emmc log ok.txt Download

Ruifeng Begin to set HS200...
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x0 SDMMC_SS_PHY_CTRL5(0x110) = 0x0
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x18c05cf000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff ff ff ff | 03 59 8f 32 00 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
CMD 21, flgs 0x358, arg 0x0, blks 1, blksz 128, timeout 150ms
CMD 21 cmplt status SUCCESS (1)
Ruifeng End to set HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x10082 SDMMC_SS_PHY_CTRL4(0x10c) = 0x102000 SDMMC_SS_PHY_CTRL5(0x110) = 0x0
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
Unable [0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
to acce[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
ss /dev/emmc0t179
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 82 00 01 00 00 00 00 00 | ff 10 ff 10 00 20 10 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e1 00 00 00 00 00 00 00

base = 0x18c05cf000 MMCSD0_HOST_CONTROL1(0x28) = 0x24 HIGH_SPEED_ENA(0x28 bit[2]) = 1 MMCSD0_HOST_CONTROL2(0x3e) = 0x8b
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 80 70 01 00 | 00 00 00 00 10 00 3a 15 | 00 09 00 00 ff ff ff ff | 03 59 8f 32 00 27 d0 00
[0x020] | 77 bb dd ee f0 00 ff 01 | 24 0b 80 00 07 00 0e 00 | 00 00 00 00 22 00 7f 03 | ff 07 ff 33 00 00 8b 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
Mounting the sd ..
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x800, blks 8, blksz 512, timeout 10000ms
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x10082 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 82 00 01 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e1 00 00 00 00 00 00 00

CMD 18, flgs 0x2000358, arg 0x820, blks 8, blksz 512, timeout 10000ms
base = 0x18c05cf000 MMCSD0_HOST_CONTROL1(0x28) = 0x24 HIGH_SPEED_ENA(0x28 bit[2]) = 1 MMCSD0_HOST_CONTROL2(0x3e) = 0x8b
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 80 70 01 00 | 00 00 00 00 10 00 3a 15 | 00 09 00 00 ff ff ff ff | 03 59 8f 32 00 27 d0 00
[0x020] | 77 bb dd ee f0 00 ff 01 | 24 0b 80 00 07 00 0e 00 | 00 00 00 00 22 00 7f 03 | ff 07 ff 33 00 00 8b 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x6820, blks 16, blksz 512, timeout 10000ms
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi：

About the CLK/CMD waveform in 400KHz mode as follows：

What do you think about the change of the HOST OUT phase before and after the A/B waveform?

Do you need more waveforms, can you tell me where you need them？

Overall waveform：

A detail waveform：

Host output waveform：

Emmc output waveform：

B detail waveform：

Host output waveform：

Emmc output waveform：

About the EMMC reading and writing test：

According to your reply, can I understand that in HS200 mode, we don't need to test the read and write TIMING of EMMC? Will this part of the TI driver be adjusted by itself?

Moreover, when the EMMC write operation is performed in HS200 mode, the probe is on the EMMC side, and there is no effect of series resistance in the middle. When a probe is connected to the CMD, the CLK will automatically change to 400KHz, and an error will be reported. There is no way to measure the CLK/CMD at 200MHz. setup hold time.

Looking forward to your reply！！

Thanks！！

0 Ruifeng Zhang over 3 years ago in reply to guo kuo

Intellectual 570 points

Hi ShiouMei,

The driver strength isn't related to the following register ? What value should it be set ?

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi：

Replenish；

(2 CMD Prior) 0 1 000110 and 0 0 000110

(1 CMD Prior) 0 1 001101 and 0 0 001101

Gated CLK

(1 CMD After) 0 1 000110 and 0 0 000110

(2 CMD After) 0 1 001101 and 0 0 001101

0 Shiou Mei Huang over 3 years ago in reply to guo kuo

TI__Genius 10180 points

Guo, Ruifeng,

You mis-understood. HS200 read timing is dynamically adjusted based on the tuning algorithm; however write timing is spec'd in the DM and the limits are defined and should be checked for compatibility with the eMMC. Lower speed modes (Legacy SDR, High Speed SDR, High Speed DDR) also have timing requirements and switching characteristics specified in the DM and should be checked if they are used.

ITAPDLY relates to the input timing and needs to be set for Legacy SDR, which is the 400 kHz speed mode you are running into issues with when the series termination resistor is soldered.

I will take a look into the waveform and logs in detail and respond with additional inquiry/ comments tomorrow.

0 Shiou Mei Huang over 3 years ago in reply to Shiou Mei Huang

TI__Genius 10180 points

Guo, Ruifeng,

SDIO1_CTRL is related to MMC1, MMC2, and not related to MMC0, which is the module you are using now.

Please provide the complete 48-bit CMD and CMD RSP for the 2 CMDs before/after the failure you observed on the scope. Your response only had 8-bits listed for each CMD and CMD RSP. This data will help isolate which CMD was causing the behavior changes in your system.

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi:

By using different methods of testing, there are several different states.

1.CLK/CMD is not connected to any external test device. If the CLK/CMD is normally powered on and started, a CMD6 error is reported in the log. As follows:

2.CLK/CMD connects to N2874A probe, and the device is powered on and started, CMD1 error will be reported in log. As follows:

3.CLK/CMD external PVP2350 probe is connected, the device is powered on and started, and EMMC device can be identified in HS200 mode, as follows:

Based on test state 3, waveform before and after Gated CLK was captured during EMMC identification. As follows:

ALL:

2 CMD Prior:

2 CMD Prior:HOST OUTPUT:0 1 000110 00000011101000010000000100000001 0101001 1

2 CMD Prior:EMMC OUTPUT:0 0 000110 00000000000000000000100100000000 1101110 1

1 CMD Prior:

1 CMD Prior:HOST OUTPUT:0 1 001101 00000000000000010000000000000000 0101001 1

1 CMD Prior:EMMC OUTPUT:0 0 001101 00000000000000000000100100000000 0011111 1

Gated CLK:

1 CMD After:

1 CMD After:HOST OUTPUT:0 1 000110 00000011101101110000001000000001 0000010 1

1 CMD After:EMMC OUTPUT:0 0 000110 00000000000000000000100100000000 1101110 1

2 CMD After:

2 CMD After:HOST OUTPUT:0 1 001101 00000000000000010000000000000000 0101001 1

2 CMD After:EMMC OUTPUT:0 0 001101 00000000000000000000100100000000 0011111 1

Do you have any problems with the above waveform and the edge state of CLK/CMD? (Measured on EMMC side)

At present, the waveform of CMD6 error cannot be captured temporarily, and the state of the probe will change when connected.

As for the waveform when CMD1 goes wrong, the software is changing the trigger mode, and then we will give feedback on this waveform capture.

Thanks!!

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Supplement：

2.CLK/CMD connects to N2874A probe, and the device is powered on and started, CMD1 error will be reported in log. As follows:

Waveform as follows:

All：

1：

2：

3：

0 Shiou Mei Huang over 3 years ago in reply to guo kuo

TI__Genius 10180 points

Guo,

Thank you for the detailed waveforms for the CMD6 failure! For the CMD1 failure, please take detailed waveforms and read out the bits like you did for CMD6.

Has your system changed recently? In your earlier message you mentioned if system is powered on without series resistors connected on CLK and CMD lines, then the CMD6 error did not happen and HS200 enumerated successfully. What changed to make this no longer the case?

CMD6 Failure

In your first example the failure happened while the system is trying to set bus width to 8. If you keep the bus width in 1 lane mode, do you see a passing behavior? Moreover, what does "CMD 6 cmplt status CMD TO ERR (5)" mean? Is it Command Timeout?

It was previously mentioned in Legacy SDR mode, the PHY_CTRL4 should be set according to the table in the DM. PHY_CTRL4[8] ITAPDLYENA = 1, [4:0] ITAPDLYSEL = 0x10. PHY_CTRL5 [17:16] SELDLYTX/RXCLK = 0x1, [2:0] CLKBUFSEL = 0x7. In your register dump they are shown as 0x0s. Please make this update.

Based on your captures, while the CLK was gated the SW likely changed the launching CLK edge from falling edge to rising edge. Thus you can see in the waveform the later CMDs are centered around the falling edge of the CLK instead of the rising edge. However, it is intriguing why this is not reflected in your register dump. Please verify if there were additional function calls between the register dump and CMD6 output.

Probe Differences

What are the difference between N2874A and PVP2350 probes?

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

Hi:

Thank you for the detailed waveforms for the CMD6 failure! For the CMD1 failure, please take detailed waveforms and read out the bits like you did for CMD6.

I think the CMD1 waveform is completely wrong. There is no way to determine from the waveform where the start and stop bits are, so there is no way to read the data.

Add series resistance to reproduce the problem. Even if the series resistance is removed, the HS200 pattern can be identified successfully, but are the above waveforms consistent? There are phase waveforms aligned with CLK rising edge and CMD jump at 400KHz, still don't understand why?

Probe Differences

What are the difference between N2874A and PVP2350 probes?

PVP2350

N2874A

Thanks!!

0 Ruifeng Zhang over 3 years ago in reply to guo kuo

Intellectual 570 points

Hi ShiouMei,

> CMD6 Failure

> In your first example the failure happened while the system is trying to set bus width to 8. If you keep the bus width in 1 lane mode, do you see a passing > behavior? Moreover, what does "CMD 6 cmplt status CMD TO ERR (5)" mean? Is it Command Timeout?

I am not very clear what you mean, do you mean not to send the command to modify the bus width?
Regarding the meaning of the error code return value 5, can you help to confirm whether it is a timeout?

> It was previously mentioned in Legacy SDR mode, the PHY_CTRL4 should be set according to the table in the DM. PHY_CTRL4[8] ITAPDLYENA = 1, [4:0] > ITAPDLYSEL = 0x10. PHY_CTRL5 [17:16] SELDLYTX/RXCLK = 0x1, [2:0] CLKBUFSEL = 0x7. In your register dump they are shown as 0x0s. Please > make this update.

I have updated the register value but it's still failed. The log is as follow when running on the LS mode.

Fullscreen EMMC_FAILED.txt Download

Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Setting environment variables...
done..
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 1 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x152, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 51, flgs 0xb58, arg 0x0, blks 1, blksz 8, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 8, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 1000ms
CMD 51 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 13, flgs 0xb58, arg 0x0, blks 1, blksz 64, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0xffffff, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0x80fffff1, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 6, flgs 0x954, arg 0x2, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status SUCCESS (1)
CMD 8 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3af0101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 17, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 60000ms
CMD 6, flgs 0x1d4, arg 0x3a10101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 17 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x0, blks 8, blksz 512, timeout 10000ms
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 13 cmplt status SUCCESS (1)
Ruifeng Set LS mode SDMMC_SS_PHY_CTRL4 & SDMMC_SS_PHY_CTRL5.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x110
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x10007
Ruifeng Begin to set HS200...
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x21c9b3c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b70201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng End to set HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x21c9b3c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b7 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
Unable [0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
to acc[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
ess /dev/emmc0t179
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set DR_TY to 4, Instead 40 Ohms.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x410000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
Mounting the sd ..
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 41 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x21c9b3c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b7 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
CMD 18, flgs 0x2000358, arg 0x800, blks 8, blksz 512, timeout 10000ms
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Ruifeng,

Even if the current register update for Legacy SDR did not resolve this current debug, these settings should be done in SW as best practices.

In my previous response there are two additional actions:

1. Based on your captures, while the CLK was gated the SW likely changed the launching CLK edge from falling edge to rising edge. Thus you can see in the waveform the later CMDs are centered around the falling edge of the CLK instead of the rising edge. However, it is intriguing why this is not reflected in your register dump. Please verify if there were additional function calls between the register dump and CMD6 output.

2. Check if bus-width = 1 worked. Right now your system is failing while trying to set bus-width = 8. This action will prove failure has no dependencies on DAT[1:7]

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

Hi ShiouMei,

Shiou Mei Huang said:
1. Based on your captures, while the CLK was gated the SW likely changed the launching CLK edge from falling edge to rising edge. Thus you can see in the waveform the later CMDs are centered around the falling edge of the CLK instead of the rising edge. However, it is intriguing why this is not reflected in your register dump. Please verify if there were additional function calls between the register dump and CMD6 output.

As we discussed before, after sending the command, it will wait for a while, and after three unsuccessful attempts, pull the GPIO high.
I can't confirm where the code position corresponds to the CLK choppy waveform. Do you have any suggestion to see what functions are called during the period?
Based on TI SDK8.0, we have not made any changes in the emmc driver part, please help to look at the code flow, thank you!

Shiou Mei Huang said:
2. Check if bus-width = 1 worked. Right now your system is failing while trying to set bus-width = 8. This action will prove failure has no dependencies on DAT[1:7]

I was skip the change bus width function, but it's still failed on CMD6.

The patch is :

@@ -928,17 +937,18 @@ static int _mmc_init_hs200( sdio_hc_t *hc, int bus_width )
 {
        sdio_dev_t              *dev;
        int                             status;
-       int                             bus_mode;
+//     int                             bus_mode;

        dev     = &hc->device;
        status  = EINVAL;

-               // set bus width
-       bus_mode        = bus_width / 4;
-       if( ( status = mmc_switch( dev, MMC_SWITCH_CMDSET_DFLT, MMC_SWITCH_MODE_WRITE, ECSD_BUS_WIDTH, bus_mode, SDIO_TIME_DEFAULT ) ) ) {
-               sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 0, "%s: switch ext_csd_bus_width (%dbit)", __FUNCTION__, bus_width );
-               return( status );
-       }
+       printf("Ruifeng Skip set bus width in %s\n", __func__);
+//             // set bus width
+//     bus_mode        = bus_width / 4;
+//     if( ( status = mmc_switch( dev, MMC_SWITCH_CMDSET_DFLT, MMC_SWITCH_MODE_WRITE, ECSD_BUS_WIDTH, bus_mode, SDIO_TIME_DEFAULT ) ) ) {
+//             sdio_slogf( _SLOGC_SDIODI, _SLOG_ERROR, hc->cfg.verbosity, 0, "%s: switch ext_csd_bus_width (%dbit)", __FUNCTION__, bus_width );
+//             return( status );
+//     }

        sdio_bus_width( hc, bus_width );

The log is:

Fullscreen EMMC_FAILED_20220602.txt Download

Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Setting environment variables...
done..
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 1 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x152, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 51, flgs 0xb58, arg 0x0, blks 1, blksz 8, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 8, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 1000ms
CMD 51 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 13, flgs 0xb58, arg 0x0, blks 1, blksz 64, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0xffffff, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0x80fffff1, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 6, flgs 0x954, arg 0x2, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status SUCCESS (1)
CMD 8 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3af0101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 17, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 60000ms
CMD 6, flgs 0x1d4, arg 0x3a10101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 17 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x0, blks 8, blksz 512, timeout 10000ms
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 13 cmplt status SUCCESS (1)
Ruifeng Set LS mode SDMMC_SS_PHY_CTRL4 & SDMMC_SS_PHY_CTRL5.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x110
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x10007
Ruifeng Begin to set HS200...
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x39cd03d000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Skip set bus width in _mmc_init_hs200
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng End to set HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x39cd03d000 MMCSD0_HOST_CONTROL1(0x28) = 0x38 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b9 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 38 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
Unable [0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
to acc[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
ess /dev/emmc0t179
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set DR_TY to 4, Instead 40 Ohms.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
SDMMC_SS_PHY_CTRL1(0x100) = 0x410000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
Mounting the sd ..
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 41 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

base = 0x39cd03d000 MMCSD0_HOST_CONTROL1(0x28) = 0x38 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b9 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 38 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
CMD 18, flgs 0x2000358, arg 0x800, blks 8, blksz 512, timeout 10000ms
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Ruifeng,

Can you dump out the register again right before Line 17 in the _mmc_init_hs200() function? Also please share the full addresses of the PHY_CTRL4, PHY_CTRL5, and HOST_CONTROL1, HOST_CONTROL2 registers you are trying to access.

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

Shiou Mei Huang said:
Can you dump out the register again right before Line 17 in the _mmc_init_hs200() function? Also please share the full addresses of the PHY_CTRL4, PHY_CTRL5, and HOST_CONTROL1, HOST_CONTROL2 registers you are trying to access.

The log is

Fullscreen EMMC_FAILED_20220607.txt Download

Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Setting environment variables...
done..
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 1 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x152, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 51, flgs 0xb58, arg 0x0, blks 1, blksz 8, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 8, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 1000ms
CMD 51 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 13, flgs 0xb58, arg 0x0, blks 1, blksz 64, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0xffffff, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0x80fffff1, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0xaaaa0000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 6, flgs 0x954, arg 0x2, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status SUCCESS (1)
CMD 8 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3af0101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 17, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 60000ms
CMD 6, flgs 0x1d4, arg 0x3a10101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 17 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x0, blks 8, blksz 512, timeout 10000ms
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 13 cmplt status SUCCESS (1)
Ruifeng Set LS mode SDMMC_SS_PHY_CTRL4 & SDMMC_SS_PHY_CTRL5.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x110
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x10007
Ruifeng Begin to set HS200...
MMCSD0_SS_CFG_base address = 0x30ca490000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_CTL_CFG_base = 0x30ca491000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng dump register in _mmc_init_hs200
MMCSD0_SS_CFG_base address = 0x30ca490000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_CTL_CFG_base = 0x30ca491000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Skip set bus width in _mmc_init_hs200
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
URuifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
nRuifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
ablCMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
e to access /dev/emmc0t179
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
Mounting the sd ..
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng End to set HS200.
MMCSD0_SS_CFG_base address = 0x30ca490000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x800, blks 8, blksz 512, timeout 10000ms
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_CTL_CFG_base = 0x30ca491000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b9 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
CMD 18, flgs 0x2000358, arg 0x820, blks 8, blksz 512, timeout 10000ms
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set DR_TY to 4, Instead 40 Ohms.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
MMCSD0_SS_CFG_base address = 0x30ca490000 SDMMC_SS_PHY_CTRL1(0x100) = 0x410000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

CMD 18, flgs 0x2000358, arg 0x6820, blks 16, blksz 512, timeout 10000ms
[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 41 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)

MMCSD0_CTL_CFG_base = 0x30ca491000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

CMD 18, flgs 0x2000358, arg 0x3820, blks 8, blksz 512, timeout 10000ms
[0x000] | 00 00 00 00 00 72 01 00 | 01 02 b9 03 00 00 1b 06 | 00 00 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x828, blks 64, blksz 512, timeout 10000ms
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
CMD 18 cmplt status SUCCESS (1)
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18, flgs 0x2000358, arg 0x868, blks 64, blksz 512, timeout 10000ms
CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x8a8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x8e8, blks 64, blksz 512, timeout 10000ms
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status CMD TO ERR (5)
cmd->opcode = 16 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status CMD TO ERR (5)
CMD 18 cmplt status SUCCESS (1)
cmd->opcode = 16 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18, flgs 0x2000358, arg 0x928, blks 64, blksz 512, timeout 10000ms
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status CMD TO ERR (5)
cmd->opcode = 16 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status CMD TO ERR (5)
cmd->opcode = 16 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x968, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x9a8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x9e8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xa28, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xa68, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xaa8, blks 64, blksz 512, timeout 10000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status CMD TO ERR (5)
cmd->opcode = 1 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xae8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xb28, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xb68, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xba8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xbe8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xc28, blks 8, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xc30, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xc70, blks 64, blksz 512, timeout 10000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xcb0, blks 64, blksz 512, timeout 10000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xcf0, blks 64, blksz 512, timeout 10000ms
CMD 1 cmplt status CMD TO ERR (5)
cmd->opcode = 1 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
CMD 18 cmplt status SUCCESS (1)
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18, flgs 0x2000358, arg 0xd30, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xd70, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xdb0, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xdf0, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xe30, blks 8, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xe38, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xe78, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xeb8, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xef8, blks 64, blksz 512, timeout 10000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xf38, blks 64, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xf78, blks 64, blksz 512, timeout 10000ms
CMD 1 cmplt status CMD TO ERR (5)
cmd->opcode = 1 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0xfb8, blks 64, blksz 512, timeout 10000ms
xpt_configure:  No sdmmc interfaces found

The SDMMC_SS_PHY_CTRL4 and SDMMC_SS_PHY_CTRL5 is offset with MMCSD0_SS_CFG_base 0x10c and 0x110.

The HOST_CONTROL1 and HOST_CONTROL2 is offset with MMCSD0_CTL_CFG_base 0x28 and 0x3e.

The debug code is

#define MMCSD0_SS_CFG_DEBUG     1
#define MMCSD0_CTL_CFG_DEBUG    1

void dump_SDMMC_SS_PHY_CTRL4_5(sdio_hc_t *hc)
{
        int i;
#if MMCSD0_SS_CFG_DEBUG
        am65x_ext_t *ext = (am65x_ext_t *)hc->bs_hdl;
        uintptr_t   MMCSD0_SS_CFG_base = ext->ss_base;

        printf("MMCSD0_SS_CFG_base address = 0x%lx SDMMC_SS_PHY_CTRL1(0x100) = 0x%x SDMMC_SS_PHY_CTRL4(0x10c) = 0x%x SDMMC_SS_PHY_CTRL5(0x110) = 0x%x\n",
                MMCSD0_SS_CFG_base,
                sdhci_in32(MMCSD0_SS_CFG_base + 0x100),
                sdhci_in32(MMCSD0_SS_CFG_base + 0x10c),
                sdhci_in32(MMCSD0_SS_CFG_base + 0x110));
        printf("Dump MMCSD0_SS_CFG...\n");

        for (i = 0; i < 0x138; i++)
        {
                if (i % 0x20 == 0)
                {
                        printf("\n[0x%03x] ", i);
                }

                if (i % 8 == 0)
                        printf("| ");

                printf("%02x ", sdhci_in8(MMCSD0_SS_CFG_base + i));
        }
        printf("\n\n");
#endif

        sdhci_hc_t              *sdhc;
        uintptr_t               MMCSD0_CTL_CFG_base;

        sdhc    = (sdhci_hc_t *)hc->cs_hdl;
        MMCSD0_CTL_CFG_base    = sdhc->base;

        printf("MMCSD0_CTL_CFG_base = 0x%lx MMCSD0_HOST_CONTROL1(0x28) = 0x%x HIGH_SPEED_ENA(0x28 bit[2]) = %d MMCSD0_HOST_CONTROL2(0x3e) = 0x%x\n",
                MMCSD0_CTL_CFG_base,
                sdhci_in8(MMCSD0_CTL_CFG_base + 0x28),
                !!(sdhci_in8(MMCSD0_CTL_CFG_base + 0x28) & (1 << 2)),
                sdhci_in8(MMCSD0_CTL_CFG_base + 0x3e));

#if MMCSD0_CTL_CFG_DEBUG
        printf("Dump MMCSD0_CTL_CFG...\n");

        for (i = 0; i < 0x268; i++)
        {
                if (i % 0x20 == 0)
                {
                        printf("\n[0x%03x] ", i);
                }

                if (i % 8 == 0)
                        printf("| ");

                printf("%02x ", sdhci_in8(MMCSD0_CTL_CFG_base + i));
        }
        printf("\n\n");
#endif
}

0 Ruifeng Zhang over 3 years ago in reply to Ruifeng Zhang

Intellectual 570 points

Hi ShiouMei,

The register physical address output as following:

SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e

The patch is :

        mem_offset64(MMCSD0_SS_CFG_base + 0x10c, NOFD, 32, &phyAddr, NULL);
        printf("SDMMC_SS_PHY_CTRL4 physical address = 0x%llx\n", phyAddr);

        mem_offset64(MMCSD0_SS_CFG_base + 0x110, NOFD, 32, &phyAddr, NULL);
        printf("SDMMC_SS_PHY_CTRL5 physical address = 0x%llx\n", phyAddr);

        mem_offset64(MMCSD0_CTL_CFG_base + 0x28, NOFD, 8, &phyAddr, NULL);
        printf("MMCSD0_HOST_CONTROL1 physical address = 0x%llx\n", phyAddr);

        mem_offset64(MMCSD0_CTL_CFG_base + 0x3e, NOFD, 8, &phyAddr, NULL);
        printf("MMCSD0_HOST_CONTROL2 physical address = 0x%llx\n", phyAddr);

0 Ruifeng Zhang over 3 years ago in reply to Ruifeng Zhang

Intellectual 570 points

Add a total of all logs:

Fullscreen EMMC_FAILED_20220622.txt Download

Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Setting environment variables...
done..
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 41 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x152, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 9 cmplt status SUCCESS (1)
CMD 51, flgs 0xb58, arg 0x0, blks 1, blksz 8, timeout 1000ms
CMD 7, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 8, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 1000ms
CMD 51 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 13, flgs 0xb58, arg 0x0, blks 1, blksz 64, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0xffffff, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0x80fffff1, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 6, flgs 0x954, arg 0x2, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status SUCCESS (1)
CMD 17, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 60000ms
CMD 17 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x0, blks 8, blksz 512, timeout 10000ms
CMD 18 cmplt status SUCCESS (1)
CMD 8 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3af0101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3a10101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
Ruifeng Set LS mode SDMMC_SS_PHY_CTRL4 & SDMMC_SS_PHY_CTRL5.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x110
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x10007
Ruifeng Begin to set HS200...
SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_SS_CFG_base address = 0x1043c9b000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
MMCSD0_CTL_CFG_base = 0x1043c9c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng dump register in _mmc_init_hs200
SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_SS_CFG_base address = 0x1043c9b000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
MMCSD0_CTL_CFG_base = 0x1043c9c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Skip set bus width in _mmc_init_hs200
CMD 6, flgs 0x1d4, arg 0x3b90201, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
UnaRuifeng End to set HS200.
bleSDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
 toSDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
 acMMCSD0_SS_CFG_base address = 0x1043c9b000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
cDump MMCSD0_SS_CFG...
e
ss /dev/emmc0t179
[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
Mounting the sd ..
MMCSD0_CTL_CFG_base = 0x1043c9c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 80 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x800, blks 8, blksz 512, timeout 10000ms
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set DR_TY to 4, Instead 40 Ohms.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_SS_CFG_base address = 0x1043c9b000 SDMMC_SS_PHY_CTRL1(0x100) = 0x410000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x820, blks 8, blksz 512, timeout 10000ms
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 41 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
MMCSD0_CTL_CFG_base = 0x1043c9c000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x8
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 80 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 08 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x6820, blks 16, blksz 512, timeout 10000ms
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18 cmplt status SUCCESS (1)
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
CMD 18, flgs 0x2000358, arg 0x3820, blks 8, blksz 512, timeout 10000ms
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms
CMD 18 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x828, blks 64, blksz 512, timeout 10000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Ruifeng,

Thanks for the updates. Reviewing your waveforms and logs again, the CMD signal was actually switched to launch off of rising edge before the gated CLK happened, instead of after as was previously mentioned. This is likely related to MMCSD0_HOST_CONTROL2 value being updated to 0x8 for V1P8_SIGNAL_ENA. Can you comment out the code that updated this register so the value will stay at 0x0?

Thanks & Regards,

Shiou Mei

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

Hi ShiouMei,

Could we switch to the 50Mhz HS mode first and then switch to the 200Mhz HS200 mode ?

How to configure it?

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

Shiou Mei Huang said:
Can you comment out the code that updated this register so the value will stay at 0x0?

Skip set the voltage to 1.8V, emmc still can't be found, the log is:

Fullscreen emmc_failed_20020627.txt Download

Starting MMC/SD memory card driver... eMMC
Starting MMC/SD memory card driver... SD
Setting environment variables...
done..
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 8 cmplt status SUCCESS (1)
CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 0 cmplt status SUCCESS (1)
CMD 8, flgs 0x152, arg 0x1aa, blks 0, blksz 0, timeout 1000ms
CMD 1 cmplt status SUCCESS (1)
CMD 8 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 55, flgs 0x151, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 1, flgs 0x12, arg 0x40000080, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 1 cmplt status SUCCESS (1)
CMD 41, flgs 0x812, arg 0x40100000, blks 0, blksz 0, timeout 1000ms
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 41 cmplt status SUCCESS (1)
CMD 2, flgs 0x72, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 2 cmplt status SUCCESS (1)
CMD 3 cmplt status SUCCESS (1)
CMD 3, flgs 0x152, arg 0x0, blks 0, blksz 0, timeout 1000ms
CMD 9, flgs 0x74, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 3 cmplt status SUCCESS (1)
CMD 9, flgs 0x74, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 9 cmplt status SUCCESS (1)
CMD 7, flgs 0x154, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 8, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 1000ms
CMD 7 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 51, flgs 0xb58, arg 0x0, blks 1, blksz 8, timeout 1000ms
CMD 51 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 13, flgs 0xb58, arg 0x0, blks 1, blksz 64, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0xffffff, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 6, flgs 0x358, arg 0x80fffff1, blks 1, blksz 64, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 55, flgs 0x152, arg 0x59b40000, blks 0, blksz 0, timeout 1000ms
CMD 55 cmplt status SUCCESS (1)
CMD 6, flgs 0x954, arg 0x2, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0, timeout 1000ms
CMD 16 cmplt status SUCCESS (1)
CMD 17, flgs 0x358, arg 0x0, blks 1, blksz 512, timeout 60000ms
CMD 17 cmplt status SUCCESS (1)
CMD 8 cmplt status SUCCESS (1)
CMD 18, flgs 0x2000358, arg 0x0, blks 8, blksz 512, timeout 10000ms
CMD 6, flgs 0x1d4, arg 0x3af0101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 18 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
CMD 6, flgs 0x1d4, arg 0x3a10101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status SUCCESS (1)
CMD 13, flgs 0x154, arg 0x10000, blks 0, blksz 0, timeout 1000ms
CMD 13 cmplt status SUCCESS (1)
Ruifeng Set LS mode SDMMC_SS_PHY_CTRL4 & SDMMC_SS_PHY_CTRL5.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x110
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x10007
Ruifeng Begin to set HS200...
SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_SS_CFG_base address = 0x4c184ca000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
MMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng mmc_init_hs200 1073 Skip set the voltage to 1.8V.
Ruifeng End to set HS200.
SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_SS_CFG_base address = 0x4c184ca000 SDMMC_SS_PHY_CTRL1(0x100) = 0x10000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x110 SDMMC_SS_PHY_CTRL5(0x110) = 0x10007
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 01 00 00 00 00 00 | ff 10 ff 10 10 01 00 00 | 07 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
MMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
MMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
Dump MMCSD0_CTL_CFG...

[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

Ruifeng Set DR_TY to 4, Instead 40 Ohms.
Ruifeng Set SDMMC_SS_PHY_CTRL4 to 0x10610f
Ruifeng Set SDMMC_SS_PHY_CTRL5 to 0x7
Ruifeng Changed HS200.
SDMMC_SS_PHY_CTRL4 physical address = 0x4f8810c
SDMMC_SS_PHY_CTRL5 physical address = 0x4f88110
MMCSD0_SS_CFG_base address = 0x4c184ca000 SDMMC_SS_PHY_CTRL1(0x100) = 0x410000 SDMMC_SS_PHY_CTRL4(0x10c) = 0x10610f SDMMC_SS_PHY_CTRL5(0x110) = 0x7
Dump MMCSD0_SS_CFG...

[0x000] | 00 4a 41 68 00 00 00 00 | 00 00 00 00 00 00 00 00 | c8 30 10 20 01 c8 ec 64 | 07 04 00 98 00 00 00 00
[0x020] | 00 00 00 00 00 01 00 00 | 04 00 00 00 02 00 00 00 | 04 00 00 00 02 00 00 00 | 01 00 00 00 00 00 00 00
[0x040] | 02 00 00 00 01 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x060] | 00 00 00 80 10 00 00 00 | 00 00 00 00 00 00 00 00 | 08 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x100] | 00 00 41 00 00 00 00 00 | ff 10 ff 10 0f 61 10 00 | 07 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | e0 00 00 00 00 00 00 00

MMCSD0_HOST_CONTROL1 physical address = 0x4f80028
UnaMMCSD0_HOST_CONTROL2 physical address = 0x4f8003e
bleMMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0
 Dump MMCSD0_CTL_CFG...
t
o acces[0x000] | 00 00 00 00 00 72 01 00 | 00 00 01 00 00 00 1a 0d | 00 09 00 00 ff db f6 ff | 03 59 0f 32 01 27 d0 00
s /dev/emmc0t179
[0x020] | 00 00 00 00 f0 00 ff 01 | 18 0b 80 00 07 fa 0e 00 | 00 00 00 00 01 00 0f 03 | ff 07 ff 33 00 00 00 00
[0x040] | 01 c8 ec 7c 07 04 00 98 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 0c 20 04 80 00 00 00 00
[0x060] | 00 01 04 00 02 00 04 00 | 02 00 01 00 00 00 02 00 | 00 00 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x080] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x0e0] | 00 01 10 01 20 01 30 01 | 40 01 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 20 4e 00 00 00 00 04 10
[0x100] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 11 4f 04 00 00 00 11 00 | 00 01 00 20 81 00 00 00
[0x120] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x140] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x160] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
Mounting the sd ..
[0x180] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1a0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1c0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x1e0] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x200] | 10 05 00 00 c8 30 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x220] | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x240] | 00 10 01 00 00 00 00 00 | 00 00 00 00 00 00 00 00 | 80 a0 f9 fd 00 00 00 00 | 00 00 00 00 00 00 00 00
[0x260] | 00 00 00 00 00 00 00 00

CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0, timeout 1000ms
CMD 6 cmplt status CMD TO ERR (5)
cmd->opcode = 6 status = 5 ====== FLIP GPIO 126
Ruifeng =======================================gpio_high=============================
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x200000
Ruifeng GPIO_OUT_DATA67 addr: 0x0060008Ch = 0x40200000

J7EVM@QNX:/# slog2info
Jan 01 00:00:00.035                       random.5                  low*     0  qcrypto: loading configuration file '/etc/qcrypto.conf' [qcrypto_common.c(190)]
Jan 01 00:00:00.036                    random.5..0                 slog*   700  Random is using the Fortuna PRNG
Jan 01 00:00:00.040                       random.5                  low      0  qcrypto: 'openssl' plugin loaded [qcrypto_plugins.c(354)]
Jan 01 00:00:00.040                    random.5..0                 slog    700  Selecting timer as an entropy source
Jan 01 00:00:00.040                    random.5..0                 slog    700  Registered path names
Jan 01 00:00:00.040                    random.5..0                 slog    700  random: starting resmgr
Jan 01 00:00:00.041                    random.5..0                 slog    700  random: Daemonizing the process
Jan 01 00:00:00.054             devb_sdmmc_am65x.9                 slog*  1800  devb-sdmmc-am65x 1.00A (May 23 2022 15:56:44)
Jan 01 00:00:00.054             devb_sdmmc_am65x.9                 slog      0  libcam.so (Sep  3 2021 11:57:38) bver 7010004
Jan 01 00:00:00.055             devb_sdmmc_am65x.9                 slog   1800  sdio_cd:  insertion path 0, cd state 0x1
Jan 01 00:00:00.056            devb_sdmmc_am65x.10                 slog*  1800  devb-sdmmc-am65x 1.00A (May 23 2022 15:56:44)
Jan 01 00:00:00.057            devb_sdmmc_am65x.10                 slog      0  libcam.so (Sep  3 2021 11:57:38) bver 7010004
Jan 01 00:00:00.057            devb_sdmmc_am65x.10                 slog   1800  sdio_cd:  insertion path 0, cd state 0x1
Jan 01 00:00:00.059                       iopkt.11          main_buffer*     0  tcpip starting
Jan 01 00:00:00.060                       iopkt.11          main_buffer      0  smmu support is disabled
Jan 01 00:00:00.061                       iopkt.11          main_buffer      0  initializing IPsec...
Jan 01 00:00:00.061                       iopkt.11          main_buffer      0   done

Jan 01 00:00:00.061                       iopkt.11          main_buffer      0  IPsec: Initialized Security Association Processing.

Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800  SD CID:
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    MID 0x1d, OID 0x4144, PNM USD
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    PRV 0x0, PSN 0x5ea8, MDT 12-2020
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800  SD CSD:
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    CSD_STRUCTURE 1, SPEC_VERS 0, CCC 0x5b5
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    TAAC 14, NSAC 0, TRAN_SPEED 50
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    C_SIZE 30719, C_SIZE_MULT 0
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    READ_BL_LEN 9, WRITE_BL_LEN 9
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    ERASE GRP_SIZE 0, GRP_MULT 0, SIZE 127
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    blksz 512, sectors 31457280, dtr 25000000
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800  SD SW CAPS:
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    bus mode 0x3, cmd sys 0x1
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    drv type 0x1, curr limit 0x1
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800    dtr 50000000
Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog   1800  CFG:  Timing HS, DTR 50000000, Bus Width 4 bit

Jan 01 00:00:00.245            devb_sdmmc_am65x.10                 slog    100  cam-disk.so (Sep  3 2021 11:57:42)
Jan 01 00:00:02.334             devb_sdmmc_am65x.9                 slog   1800  sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 6, flgs 0x1d4, arg 0x3b90101, blks 0, blksz 0
Jan 01 00:00:02.334             devb_sdmmc_am65x.9                 slog   1800  mmc_init_hs: switch ECSD_HS_TIMING HS
Jan 01 00:00:03.449             devb_sdmmc_am65x.9                 slog   1800  sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 16, flgs 0x154, arg 0x200, blks 0, blksz 0
Jan 01 00:00:03.449             devb_sdmmc_am65x.9                 slog   1800  mmc_init_bus: sdio_set_block_length
Jan 01 00:00:03.582                tisci_mgr.36877                 slog*    55   SYSFW Firmware Version 21.5.0--v2021.05 (Terrific Llam
Jan 01 00:00:03.582                tisci_mgr.36877                 slog     55   SYSFW Firmware revision 0x15
Jan 01 00:00:03.582                tisci_mgr.36877                 slog     55   SYSFW ABI revision 3.1
Jan 01 00:00:03.590           shmemallocator.49166                 slog*     0  SharedMemoryAllocator: BaseAddress: 0xb8000000 Size: 0x20000000 (536870912)

Jan 01 00:00:03.590           shmemallocator.49166                 slog      0  SharedMemoryAllocator: BaseAddress: 0x00000000 Size: 0x00000000 (0)

Jan 01 00:00:03.761                tiipc_mgr.53263                 slog*     0  [IPC]
Jan 01 00:00:03.761                tiipc_mgr.53263                 slog      0  Mailbox_plugInterrupt: interrupt Number 489, arg 0xAA3CC738

Jan 01 00:00:03.776                tiipc_mgr.53263                 slog      0  [IPC]
Jan 01 00:00:03.776                tiipc_mgr.53263                 slog      0  Mailbox_plugInterrupt: interrupt Number 490, arg 0xAA3CC8D8

Jan 01 00:00:03.792                tiipc_mgr.53263                 slog      0  [IPC]
Jan 01 00:00:03.792                tiipc_mgr.53263                 slog      0  Mailbox_plugInterrupt: interrupt Number 491, arg 0xAA3CCA78

Jan 01 00:00:03.807                tiipc_mgr.53263                 slog      0  [IPC]
Jan 01 00:00:03.807                tiipc_mgr.53263                 slog      0  Mailbox_plugInterrupt: interrupt Number 492, arg 0xAA3CCC18

Jan 01 00:00:03.822                tiipc_mgr.53263                 slog      0  [IPC]
Jan 01 00:00:03.822                tiipc_mgr.53263                 slog      0  Mailbox_plugInterrupt: interrupt Number 493, arg 0xAA3CCDB8

Jan 01 00:00:04.157                   screen.61457                 slog*   300  screen: starting up...
Jan 01 00:00:04.159                   screen.61457                 slog    300  screen: Configuration file:  /ti_fs/usr/lib/graphics/jacinto7/graphics.conf.dss_on_r5
Jan 01 00:00:04.305                   screen.61457                 slog    300  screen: slog2 context created with 1 pages
Jan 01 00:00:04.305                   screen.61457                 slog    300  screen: loading alloc module stdbuf...
Jan 01 00:00:04.307                   screen.61457                 slog    300  screen: display 1 returned invalid value 0 for WFD_PORT_MODE_ROTATION_SUPPORT
Jan 01 00:00:04.309                   screen.61457                 slog    300  screen: loading libhiddi.so...
Jan 01 00:00:04.309                   screen.61457                 slog    300  screen: server is ready
Jan 01 00:00:04.571             devb_sdmmc_am65x.9                 slog   1800  sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0
Jan 01 00:00:05.586             devb_sdmmc_am65x.9                 slog   1800  sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0
Jan 01 00:00:06.601             devb_sdmmc_am65x.9                 slog   1800  sdio_wait_cmd: TIMEOUT 1000ms (errno 260) CMD 0, flgs 0x1, arg 0x0, blks 0, blksz 0
Jan 01 00:00:06.601             devb_sdmmc_am65x.9                 slog   1800  sdio_cd:  Unsupported card inserted

Ruifeng mmc_init_hs200 1073 Skip set the voltage to 1.8V.
MMCSD0_CTL_CFG_base = 0x4c184cb000 MMCSD0_HOST_CONTROL1(0x28) = 0x18 HIGH_SPEED_ENA(0x28 bit[2]) = 0 MMCSD0_HOST_CONTROL2(0x3e) = 0x0

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Ruifeng,

Can you capture the same CLK, CMD, DAT0 waveforms again? Do you see CMD launching off of rising edge now after V1P8_SIGNAL_ENA is disabled? Moreover, it looks like in your log you had some other crashes. Are you able to produce a clean log after PORz or does the same crash happen every time?

You can change speed mode to High Speed by modifying the arch/arm64/boot/dts/ti/k3-j721e-main.dtsi, locate main_sdhci0 and comment out the lines defining mmc-ddr-1_8v and mmc-hs200-1_8v.

0 Ruifeng Zhang over 3 years ago in reply to Shiou Mei Huang

Intellectual 570 points

> You can change speed mode to High Speed by modifying the arch/arm64/boot/dts/ti/k3-j721e-main.dtsi, locate main_sdhci0 and comment out the lines defining mmc-ddr-1_8v and mmc-hs200-1_8v.

I mean in one boot, switch to HS mode first, then switch to HS200 mode. The OS is qnx, which parameter need to be changed ? Thanks.

I will capture the waveforms on the version that V1P8_SIGNAL_ENA disabled and share to you later.

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Ruifeng,

For QNX driver update, please contact QNX directly.

0 guo kuo over 3 years ago in reply to Shiou Mei Huang

Prodigy 160 points

HI;

CLK, CMD, DAT0 waveforms.

YELLOW:CLK

PINK:CMD

BLUE:DAT0

GREEN:GPIO

0 Ruifeng Zhang over 3 years ago in reply to guo kuo

Intellectual 570 points

Hi ,

Please help to parse this waveform and register dump when skip set the voltage to 1.8V. Thanks.

Another question:

We would like to know what actions/commands are sent by the emmc controller during the transition from 400k to high-speed mode (50M/200M), and what is the function?
During the mode switching process, does the EMMC still have data transmission? How to ensure the stability of the data when the frequency is switched?

0 Shiou Mei Huang over 3 years ago in reply to Ruifeng Zhang

TI__Genius 10180 points

Ruifeng,Guo,

It's hard to understand what is happening on the bus based on the waveform, can you read out the bits like you did before? It does look like the CMD is launched off of the falling edge now, is this correct?

As for what the eMMC controller is doing, that is very driver specific. Please consult QNX on that aspect since you are using their driver code. Typically data transactions are paused until the handshaking is completed, and mode switching would be considered a part of handshaking sequence.