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ARM cache problems on OMAPL137

Maxime Renaudet
Intellectual 510 points
Other Parts Discussed in Thread: OMAP-L137

Hey everyone,

 

So I've been working on understanding how cache works on OMAP l137 on the ARM side.

I think I got almost all of it. But one think I can't figure out is why it's crashing when I put code and data in DSP L1 (P: 0x11E0 0000, D:0x11F0 0000) or DSP L2 memory (0x1180 0000). As soon I enable MMU, it seems like ARM can't access these memory areas anymore.

This kind of problem doesn't happen when I enable MMU and code and data are in Shared Ram (0x8000 0000) or in External SDRAM (0xC000 0000) and run with MMU fine. Although MMU configuration is done the same way ...

 

Does anyone have any idea about this ? Is DSP Ram not cacheable the ARM core ?

Thanks

  • 0
    TI__Genius 14545 points

    Maxime,

     

       Do you have the DSP L1/L2 Configured as cache? Also - can you confirm DSP Megamodule powered up?

    Section 5.3 of the OMAP-L137 System Reference Guide says the following.

    "The DSP internal memories are accessible by the ARM and other master peripherals (as dictated by the
    connectivity matrix) via the system interconnect through the DSP SDMA port. The accesses by the DSP to
    its internal memory are internal to the DSP subsystem and do not go out on the system interconnect."

    This implies that the C674x DSP Megamodule is powered up. The shared RAM is globally accessible. Perhaps this is the reason you program is crashing when you try to access the DSP memories using the ARM.

  • 0 in reply to dabuan
    Intellectual 510 points

    Heyn

     

    No, DSP L1/L2 are not configured as cache, the problem is not accessing these two areas of memory.

    I can access them without any problem, the only problem is when I try to cache in ARM cache these memory areas. I configure everything (write tables, Set CP15 register C2 with page table base address, then CP15 register C3 with domain access, set bit C, M and I in CP15 register C1 ... Anyway I doubt my configuration is wrong since it works with other memory placement such as Shared Memory and External Memory SDRAM). But as soon I enable MMU it can't read DSP L1/L2 ...

     

    Thanks

     

    BR


    Maxime