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Cache_wb - dosent work as expected

Sujith
Genius 12455 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

Problem : In the driver i am working i would require to writeback to memory from cache. I use the function Cache_wb () to do so. The buffer that requires to be written back could be from the non-chached section or cached section (Driver will not have control over this, this buffer would be supplied by the applications)

Observation: The function never returns, seems to stuck in some loop waiting for (attached is the image on CCSV5 when stopped)

Could we call cache validate / invalidate / write back on non-chached memory segments, what else could be wrong? Following are the configurations details

1. Platform - DM814x - M3 ISS core

2. BIOS Version - bios_6_31_04_27

3. XDC Tools - xdctools_3_20_08_88

Thanks, Sujith

  • 0
    TI__Mastermind 30830 points

    I can't find the attachment you refer to. Can you describe the loop that the M3 is stuck in?

    I believe cache operations performed on non-cached regions are legal, although meaningless. I'll check into this to confirm.

     

    Alan

  • 0 in reply to Sujith
    TI__Mastermind 30830 points

    The core is waiting for the other core to release the Gate shared between the two cores that arbitrates access to the unicache registers.

    Are both cores running?

    Which core is configured to initialize the AMMU and enable the unicache?

    Alan

     

  • 0 in reply to Alan DeMars
    TI__Genius 12455 points

    Alan,

    A8 setsup the MMU and Ducati M3 (ISS) enables the unicache). Attached are the gel files that i used. Initializations are done on connect target.

    Thanks, Sujith

    2100.gelFiles.zip

  • 0 in reply to Sujith
    TI__Mastermind 30830 points

    Are you only running one core?

    If so, try adding this to your config script:

     var GateDualCore = xdc.useModule('ti.sysbios.family.arm.ducati.GateDualCore');

     GateDualCore.initGates = true;

    This will make sure that the Gate used to arbitrate access to the unicache registers gets initialized.

     

    Alan

  • 0 in reply to Alan DeMars
    TI__Genius 12455 points

    Alan,

    I hit a compilation error when i tried to initialize the gates as you have specified

    # Invoking configuro...

    a+x E:/git_hdvpss/netra-video/pspdrivers_/build/maketemp_configuro_cmd_m3vpss.bat

     

    E:\git_hdvpss\netra-video\pspdrivers_\packages\ti\psp\examples\common\vps\chains>E:/installedtools/TI/xdctools_3_20_08_88/xs xdc.tools.configuro --generationOnly -o E:/git_hdvpss/netra-video/pspdriver

    s_/build/hdvpss_examples_chains/obj/ti814x-evm/m3vpss/whole_program_debug/hdvpss_examples_chains_configuro -t ti.targets.arm.elf.M3 -p ti.platforms.evmDM8148:core1 -r whole_program_debug -b E:/git_hdv

    pss/netra-video/pspdrivers_/packages/config_ti814x.bld vpsChains.cfg

    making package.mak (because of package.bld) ...

    js: "E:/git_hdvpss/netra-video/pspdrivers_/packages/config_ti814x.bld", line 14: XDC runtime error: ti.sysbios.family.arm.ducati.GateDualCore: no element named 'initGates'

        "./config.bld", line 3

    xdctools_3_20_08_88\gmake.exe: *** No rule to make target `linker.cmd'.  Stop.

    js: "E:/installedtools/TI/xdctools_3_20_08_88/packages/xdc/tools/Cmdr.xs", line 51: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.

    gmake[1]: *** [xdc_configuro] Error 1

    gmake: *** [chains] Error 2

    bash-3.1$

    Thanks, Sujith

  • 0 in reply to Sujith
    TI__Mastermind 45025 points

    Sujith,

    Based on the error, it looks like you added the lines that Alan mentioned to the file config.bld.  If so, this is not the correct place to add them.

    Can you try adding those lines to your configuration script? (it will have a .cfg extension.)

    Steve

  • 0 in reply to Steven Connell
    TI__Genius 12455 points

    Steve / Alan,

    Thanks this works.

    Sujith