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end address for DMA

Jim16302
Prodigy 90 points

I am reading the DMA spec for c5505, which provide registers to program start addresses in internal memory. How about end addresss?  I would like to have the DMA read data continuously from the start address to the end address, then then automatically go back to the start address, like a continuous loop reading. Can C5505 do this?

Thanks,

Jim

  • 0
    TI__Mastermind 30110 points

    Hi Jim,

     

    The DMA of the C5505 can perform continuous loop reading of a block of memory as you described.

     

    Instead of specifying the start and end addresses for a DMA transfer, you should specify the start address and the transfer length of the transfer.

    “Load the DMA transfer control register 1 (DMACHmTCR1) with the number of double words to transfer. Note that the number of double words must be specified in bytes. For example, for a 256 double word transfer, program this field with 1024 (256 x 4 = 1024).” (See 2.12 Initialization and 4.3 Transfer Control Registers in the C5505 DMA User’s Guide)


    To perform continuous loop reading, you need to configure the DMA for auto-initialization. You will need to set SYNCMODE = 1 and AUTORLD = 1 within the DMACHmTCR2 register. (See 2.8 Channel Auto-Initialization Capability in the C5505 DMA User’s Guide)

     

    The USB_Stick_AudioFilter1.zip on our C5505 eZdsp Google Code Page demonstrates the use of DMA to transfer between the AIC3204 codec and DARAM.

    Also, the C5505 Chip Support Library (C55XCSL-LOWPOWER) contains three DMA examples that may help you become an expert on the C5505 DMA.

     

    Hope this helps,

    Mark

  • 0 in reply to Mark M
    Prodigy 90 points

    Thanks, Mark. That is the information I was looking for .

    Jim

  • 0 in reply to Mark M
    Prodigy 90 points

    Hi,  Mark,

               I've got  one more more question on this:  I am using 5505's DMA for its I2S interface, which is connected to a dual ADC.    Following is the connection.

     

                                         I2S0_CLK -----------------> SCLK                                         <----- ADC In 0

    5505  (DMA0<-->I2S)        I2S_FS      -----------------> FS              Dual Channel ADC     <----- ADC In 1

                                         I2S_RX     <----------------- DOUT

                                         I2S_DX     -----------------> DIN

     

               The application is to ping-pong the ADC sampling (ADC In 0, ADC In 1, ADC In 0, ADC In 1, ADC In 0, ...).  I plan to use  one channel of DMA for receive and another channel for transmit (controlling the channel selection in ADC for each sample).  My question is:

                      Can this connection work?  DMA need to keep up with the strict sequencing requirement, i.e.   DMA channel 0 (transmit), channel1 (receive), channel 0 (transmit), channel1 (receive), channel 0 (transmit),...                 

    Thanks,

    Jim 

     

     

     

  • 0 in reply to Jim16302
    Guru 14640 points

    All:

    I have a similar situation - except the ADC has 4 inputs, and the address for the "next" input is output at the time of reading in the present value.

    So, if I was reading 4 inputs from the ADC, I would set it up as follows:

    1. Send  addr 0,  read addr 3 (except first time)

    2. Send addr 1, read addr 0.

    3. Send addr 2, read addr 1.

    4. Send addr 3, read addr 2.

    5. DMA resets back to step 1.

    -----------------------------------------------------

    I have DMA-I2S code that does the above.

     

    I can also read 2 inputs from the ADC - essentially the length is half of the value used for 4 inputs.

     My setup is shown below...

    chanNum = CSL_DMA_CHAN1;

    dma_w.Config.pingPongMode = CSL_DMA_PING_PONG_DISABLE;

    dma_w.Config.autoMode = CSL_DMA_AUTORELOAD_ENABLE;

    dma_w.Config.burstLen = CSL_DMA_TXBURST_1WORD;

    dma_w.Config.trigger = CSL_DMA_EVENT_TRIGGER;

    dma_w.Config.dmaEvt = CSL_DMA_EVT_I2S0_TX;

    dma_w.Config.dmaInt = CSL_DMA_INTERRUPT_DISABLE;

    dma_w.Config.chanDir = CSL_DMA_WRITE;

    dma_w.Config.trfType = CSL_DMA_TRANSFER_IO_MEMORY;

    dma_w.Config.dataLen= 8; // =8 for 4 commands

    dma_w.Config.srcAddr= (Uint32)cmd_buf;

    dma_w.Config.destAddr = (Uint32)(0x2808);

     

    dma_Handle= dma_drv_Config(&dma_w);

     

    My dilemma - I need to output 3 requests for ADC data, not 2 or 4. When I place a value of 6 in the length field, I do not get the 3 requests...

    Is this a limitation of the DMA controller? From my reading, it looks like you can have burst modes of 1,2,4,8 ... is 6 impossible to do?

    Regards,

    Todd Anderson

  • 0 in reply to Todd Anderson78572
    Guru 14640 points

    All:

    I figured out the problem with my setup, with some helpful thoughts from our supporting Field Applications Engineer. It turned out that my I2S setup needed to be changed, and now I am able to output 3 requests for ADC data.

    Regards,

    Todd Anderson