clkmd PLL adjusting for High speed, PLL problem. Unstable code

Is there a smaller PLL MULT value than 17 that works, other than what you indicate above with 01010b (x10)?

As you indicated above, the resultant PLL output frequency is 204MHz, which is 4MHz higher than what the device is characterized to support.  The VC5509A is rated at 200MHz maximum.

Actually in our lab works, we built ONE board (ıt is our first test drive card). When we were sure that this card was working properly we started to design our software based on 204MHz (Our delays, timers, FFT processes etc) and sent the card  to the serial production We encountered some reset situations, some debug problems, software hangs problems and started to investigate the core problem and looked nearly all of the IC pins on board, the core voltage and IO voltages on card, 12Mhz clock frequency. Everything is OK. Then I changed the PLL frequency just to try and everything was OK. So I started to decrease the PLL mult from 17 one by one. And I see that pll mult : 10 is the minimum working frequency of this card. Of course I could set this value below 10. But I couldnt set it above 10.

DSP pdf could say that 204 is the mazimum freq but actually I could run the boards on 280 Mhz  on the fitst test drive card :)   -- OverClocking the DSPs

saltan said:

Actually in our lab works, we built ONE board (ıt is our first test drive card). When we were sure that this card was working properly we started to design our software based on 204MHz (Our delays, timers, FFT processes etc) and sent the card  to the serial production We encountered some reset situations, some debug problems, software hangs problems and started to investigate the core problem and looked nearly all of the IC pins on board, the core voltage and IO voltages on card, 12Mhz clock frequency. Everything is OK. Then I changed the PLL frequency just to try and everything was OK. So I started to decrease the PLL mult from 17 one by one. And I see that pll mult : 10 is the minimum working frequency of this card. Of course I could set this value below 10. But I couldnt set it above 10.

What core voltage is being supplied to the C5509A on the CVdd pins?  In order to support 200MHz, CVdd needs to be 1.6V. 

You would please cite the document and where in the document you find the 204MHz operation?

I think this goes without saying, that although you may have found bench experiments that a particular device can support >200MHz, you should not rely on this for your application.  The devices will only be characterized to 200MHz operation.

BrandonAzbell

The main problem is not 200 Mhz  + 4 MHz. The main problem is I don't want to run the C5509A on 120 MHz. It is a low speed for the application. It can 180, 192, or 200 MHz.  But our card can not exceed 120 MHz. I want to understand why this is happening on our board. Every IC on board, EMIF interface, SPI interfaces, CODEC interfaces, audio processes are runnunig on 120MHz. But when I change it to the nearest high PLL Mul: 11 It means 132 Mhz, the code hangs. ( I tried all of the PLL Mult above 10)

Yes the core voltage is 1.6V. But in my opinion this core voltage is another bench topic. Let me clear this.

1. When the cpu is in idle state I set the core voltage to 1.6V

2. When I encountered this ridicilious problem on PLL, I thought there ,s a core voltage problem. So I measured the core voltage, while the code was very active  process. I see that this voltage was less than when the cpu was in idle state. So I adjusted the core voltage to 1.6V when the code is running. But with this adjusment, idle core voltage is 1.714V. I know it shouldn't exceed 1.65V but put yourself  to me if you have such a ridicilious situtaion.

3. In the sentence "DSP pdf could say that 204 MHz" must be 200 MHz. It was my copy-paste mistake. Sorry for this.

Do you happen to have an EVM for the 5509A to compare results?

There are many potential causes for your problem.

A) One potential problem is that your custom board is not designed properly, and that is why 120 MHz is your maximum speed.  The fact that your 1.6V power supply cannot maintain voltage regulation with a high current draw is a strong indication that you need to redesign the power circuits.  Increasing the voltage is not a valid solution for bad regulation, as you have noticed when it produced 1.714V under light loads.  I suggest that you use the TPS76316. It will maintain 1.6V regulation to 150 mA, which is well over the 120 mA draw that the 5509A will take at its maximum 200 MHz.

B) A slightly less likely issue is that your code has a bug in it which only manifests at speeds above 120 MHz.  As suggested, you should try the Evaluation board running your same code to see if it even works at full speed on a board with no circuit design errors.  Perhaps your code is in a deadlock due to the higher speed, and it's not the chip.

C) The least likely cause is a bad chip or bad PLL. This same chip PLL works on other boards.