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Efficient use of C6455+ SRIO with EDMA

Joseph Gagnon
Prodigy 200 points
Other Parts Discussed in Thread: TMS320C6455

I am attempting to establish an SRIO data communication infrastructure that will split a large data block into multiple LSU-sized parcels and make the most efficient use of the SRIO bandwidth possible with minimal DSP resources consumed. I will be using all 4 LSUs with NWRITE_R to ensure data integrity while not stalling the transfer to wait for a single LSU to complete. This will require noticable DSP resources to handle the LSU parcel completion interrupts.

I was hoping to set up a the DSP EDMA to populate the control registers of all 4 of these LSUs as they interrupt but all of the examples strongly imply that the C6455 can only support one EDMA-LSU-interrupt connection.

Q1) Is this correct?

Q2) If this is correct, is it a hardware connection to a specific LSU or is it merely a correlation limitation where the EDMA can only listen to one LSU interrupt at a time but that LSU can be any of the 4 available?

Q3) If it is a hardware connection to a specific LSU, which one?

If you locate this information in a document please include a reference to the document (both TI code name and verbose name, ideally).

Thank you in advance,

Joseph Gagnon

Dyaptive Systems

  • 0
    TI__Guru* 84110 points

    Joseph,

    Which documents have you looked in? I would expect the datasheet, the EDMA3 User's Guide, and the Serial RapidIO User's Guide would be the ones with this information. You can find all of them on the TMS320C6455 Product Folder.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 200 points

    I have consulted several resources that I will list below.

    Forums:

    • http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/71298/258718.aspx
    • http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/p/11391/145624.aspx
    • http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/11539/327466.aspx

    Documents:

    EDMA Controller (spru966b.pdf)

    SRIO User Guide (spru976e.pdf)

    C6455 Datasheet (sprs276k.pdf)

    several others such as "External Programming of the EDMA device (spraa34.pdf)"

    Examples:

    DIO_lib

    • testDIO_edmaStreamLsu
    • RIO_EdmaStreamingLsu
    • RIO_EdmaStreamNum

     

    As I mentioned in my original message, I was able to find strong indications in the demos of the general status but nothing to help me determine the answers to all of my questions.

    Specifically the EDMA only has one interrupt in from the SRIO but I wasn't able to establish the LSU side of the wiring: it could fire when one LSU interrupt fires but which one could be hardwired; it could fire when one LSU interrupt fires but which one could be configurable; or it could fire when any LSU fires with no ability to limit it to only fire when a particular LSU fires and not fire when the other LSUs fire. This is an important distinction for my purposes.

    My current understanding is that the INTDST1 routed to the EDMA is driven by an OR of all 4 LSU interrupts. This would mean that if I want to use all 4 LSUs (a high priority) I must forgo using the EDMA to load the control registers of any of them (a moderate priority).

    I am hoping that I am incorrect and would greatly appreciate clarity in this regard.

    Thank you,

    Joseph Gagnon

    Dyaptive Systems

     

  • 0 in reply to Joseph Gagnon
    TI__Guru* 84110 points

    Joseph Gagnon,

    The documents you have looked at have the sum of the information available.

    The SRIO module has eight (8) INTDST lines that it can generate, but the datasheet shows that for the C6455 only four (4) are connected inside the device. The registers associated with the others could still be used in a polling environment, but not as interrupt or event signals.

    INTDST0, INTDST1, and INTDST4 are routed to the DSP interrupt controller. Further refinement of the interrupt source can be done in the DSP's Interrupt Service Routine by examining the SRIO registers.

    INTDST5 is routed to the MAX Reset signal.

    INTDST1 is routed to the EDMA3 event logic, in addition to going to the DSP INTC.

    Joseph Gagnon said:
    My current understanding is that the INTDST1 routed to the EDMA is driven by an OR of all 4 LSU interrupts.

    If something in the documentation led you to this understanding, please let us know where that is so we can check the wording.

    Each LSU, and several other SRIO components, has an ICRx register that allows it to route that LSU's (or other component's) interrupt to any of the eight (8) logical INTDSTn signals.

    You can route each LSU interrupt to a different INTDSTn from the peripheral, but only the one INTDST1 is routed to the EDMA3. 

    If you select INTDST1 for all of the LSUs, then the INTDST1 to the EDMA3 will be the logical OR of those 4 LSU interrupts. But there is no mechanism designed into the C6455 SRIO or EDMA3 to allow you to discriminate between the 4 LSU sources using only the EDMA3 event.

    The only clean and robust method is what the DIOLIB uses, with EDMA3 driving data to a single LSU.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • 0 in reply to RandyP
    Prodigy 200 points

    RandyP said:

    My current understanding is that the INTDST1 routed to the EDMA is driven by an OR of all 4 LSU interrupts.

    If something in the documentation led you to this understanding, please let us know where that is so we can check the wording.

    [/quote]

    Thank you for clarifying, the source of my confusion in this regard was in the SRIO User Guide (spru976e.pdf) pg 104 where it refers to the LSU bit (bit 31) generation at the top of the page. Given the clarification you have provided I presume this means the 8-bit set for the LSU directed at the INTDSTx in question rather than all 32 bits of the ICSR. I've quoted below for your reference.

    "Bits within the LSU interrupt condition status register (ICSR) are logically grouped for a given core and ORed together into a single bit (bit 31) of the decode register"

    Thanks RandyP,

    Joseph Gagnon

    Dyaptive Systems

  • 0 in reply to Joseph Gagnon
    TI__Guru* 84110 points

    I believe we are in agreement on the operation now.

    As an example:

    LSU1's interrupt is mapped to INTDST0 to cause DSP interrupt 11.
    LSU2's interrupt is mapped to INTDST1 to cause an EDMA3 event trigger.
    LSU3's interrupt is mapped to INTDST4 to cause DSP interrupt 12.
    LSU4's interrupt is also mapped to INTDST4 to cause DSP interrupt 12.

    Any of the 8 bits for LSU1 in LSU_ICSR will cause INTDST0 to be asserted which will then cause DSP INT11, for this example.
    Any of the 8 bits for LSU2 in LSU_ICSR will cause INTDST1 to be asserted which will then cause an EDMA3 event trigger, for this example.
    Any of the 8 bits for LSU3 OR any of the 8 bits for LSU4 in LSU_ICSR will cause INTDST4 to be asserted which will then cause DSP INT12, for this example.

    If you mapped all four LSU's to INTDST1, then any of the 32 bits in LSU_ICSR would cause an EDMA3 event. But the EDMA3 cannot discriminate between the different causes of the event nor between the different LSUs. So it would be difficult to put together a convenient method for responding to the same event for multiple LSUs.

    The best choice would be to use a highly optimized ISR that could service INTDST0 or INTDST4 and determine the interrupt source, then respond by manually triggering a DMA event to service the next part of the block.

    I do not have an example of this, and it is left as an exercise to whoever wants it.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.