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DRA821U: Packet Loss observed when 1Gbps Full traffic load

Jack
Mastermind 9105 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821,

Hi Champs

There's an issue that a customer wants to solve about CPSW-5g and SGMII.

Three PHYs were connected through SGMII as below.

Test Conditions :

1. All the SGMIIs are connected to the Capacitor 100nF.

2. All PHY inputs and outputs consists of CML circuit.

3. SDK version : PSDK v8.1

4. Traffic load uses Spirit C1 equitment.

Issues 1. (100Base-T1 related)

Scenario #1

- Path : A72 -  CPSW - PHY - PC

- Problem : During the two-way test of ping between ARM and PC, the path of 100M PHY is packet loss. However No packet loss when using other 1G PHYs.

Scenario #2

- Path : 1G PHY #1 - CPSW - 100M PHY

- Problem : Packet loss occurs when transmitting and receiving 100Mbps of traffic.

- Remark : Only occurs in the 1G PHY -> 100M PHY direction

Attachments : 

- after AP_CAP  : DRA821 output waveform

- after PHY_CAP : DRA821 input waveform

Issues 2. (1000Base-T1 related)

- Path : 1G PHY #1 - CPSW - 1G PHY #2

- Problem : When Full traffic load of 1Gbps, Packet loss occurs only at CPSW output terminal even though CPSW input terminal does not have packet loss.

 

Common Info :  Line loopback test of all PHYs confirmed no problem.

They believed the above issues appear to be related to the SGMII interface and CPSW

According to them, the strange thing is that if you test the speed at 999Mbps instead of 1Gbps, there will be no issue.

Please help and review as soon as possible.

Regards, 

Jack

  • 0
    TI__Mastermind 23125 points

    Jack, 

    a few quick questions about the test setup:

    1. can you give part numbers of the 100M and 1G PHYs? 

    2. is the PC a 1Gbps port?

    3. on Scenerio 2, did they ping from one MAC to another MAC, from the same DRA821 device?

    Jian

  • 0 in reply to jian35385
    Mastermind 9105 points

    Hi Jian. 

    They're using it as follows.

    - 100M PHY : Marvell 88Q1111

    - 1G PHY : Marvell 88Q2221

    - PC : 100/1000Base-T

    They would like to know how to check if ehthernet switch f/w works fine. 

    Regards, 

    Jack

  • 0 in reply to Jack
    Mastermind 9105 points

    Hi Jian

    Can you please let us know how to check if MAC receive and transmit the packets without loss?

    They need the debug guideline from the DRA821U point of view. e.g. tool, procedure and so on.

    Regards, 

    Jack

  • 0 in reply to Jack
    Mastermind 9105 points

    Hello TI CPSW Team

    Can we expect any suggestion on this? e.g. Guidance, Status, Something else. 

    Regards, 

    Jack

  • 0 in reply to Jack
    Mastermind 9105 points

    Hi TI

    There're some update from Customer experiments on this thread.

    1. Packet Loss disappeared when changed OSC0 19.2MHz with +-3ppm tolerenace part.

    They observed the packet loss problem has not been reproducible when 1G to 1G use case with packet size 64byte for 5 hours after changed OSC0 19.2MHz clock with very small frequency tolerance range within +/-3ppm which can not be applicable to their mass production due to delivery issue. 

    The issue comes out when using +-50ppm tolerance with the specification below. it's from chinese supplier.

    They believe that even though the packet loss does not occur under the current conditions, production is not possible.
    They would like to ask you to check additional parts that you can try while showing this pattern.

    2. SGMII Test Report Request

    Currently, EVM Kit is designed as QSGMII, but we use it as SGMII.
    I would like to check and share the results of the SGMII performance test if they exist inside the TI.

    3. Check if OSC1 clock is mandatory

    - DATASHEET says the use of OSC1 for Main Domain
    - EVM Kit shows as optional usage
    - According to the Ref manual, Need to select btw OSC0 and OSC1 and mark it as if only one is used

     

    We woule appreciate if you give the prompt response on this.

    Thanks.

    Regards, 

    Jack

  • 0 in reply to Jack
    Mastermind 9105 points

    Hi Ti

    There's a request on this issue.

    Customer has identified the issue(1Gbps-To-1Gbps) could not be reproducible when they applied 25.000625MHz with +PPM specification.

    However it's difficult to use +PPM part for their mass product due to supply issue.

    To avoid the packet loss issue, Please give TI' recommendation from Jacinto design team or official headquarter on this. 

    Thanks.

    Best Regards, 

    Jack

  • 0 in reply to Jack
    Mastermind 9105 points

    Hi TI

    Here's organized summary regarding their test case as below figure.

    Except 1G to 1G test case, there're still the packet loss issue and FCS error are observed as above when a sgmii port is configured for 100Mbps.

    Thanks.

    Regards, 

    Jack

  • 0 in reply to Jack
    Mastermind 9105 points

    Hi TI

    Please take care of this issue with higher pririty. Thx

    (1G to 1G issue is resolved by replacing 19.2MHz clock with +ppm. 100M to 100M/1G mode is still failure)

    We're waiting for EVM Test Result from Customer to see if the same issue is reproducible. Thx.