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AM6528: EtherCAT master and slave on the same chip

michele sponchiado
Prodigy 10 points
Part Number: AM6528
Other Parts Discussed in Thread: AM2434

Dears sirs,

we are evaluating if it is possible to implement on the same chip both:

  • an EtherCAT master for a local network
  • an EtherCAT slave toward a higher level EtherCAT network

We know that the AM64x/AM65x series can implement both the EtherCAT master and the slave.

QUESTION: is it possible to have both the stacks (master and slave) on the same chip running at the same time?

QUESTION: if yes, is the same feature possible even on the AM24x (e.g.: AM2434) series?

Best regards

Michele Sponchiado

  • 0
    Mastermind 7490 points

    Hi,

    I'm not TI, but I've been working with the AM6* chips for quite some time now, and we offer an EtherCAT master that runs on the AM64x (https://www.ibv-augsburg.de/icnet/ethercat-master/). AFAIK there's no master stack from TI, only from third parties.

    Yes, you can have a master and a slave running on the same chip, even on the AM24x.

    Of course it depends on the details:

    • you need an ICSSG for the EtherCAT slave firmware, and you need an R5f core for the slave stack.
    • you need either another ICSSG or the CPSW for the EtherCAT master, plus a core that runs the master stack.
    • depending on the cycle times you're hoping to achieve there could be further requirements, e.g. to use a dual R5f subsystem in single-core mode to get the doubled TCM size to improve execution of the slave stack code

    Regards,

    Dominic

  • 0 in reply to Dominic Rath
    Prodigy 10 points

    Hi, Dominic!
    Many thanks for your reply!

    The firm I am consulting needs to develop both an axis control board and a CCU that, as said, should act both as master and slave EtherCAT.

    My idea is to implement a core board based on the AM2434, that, when coupled with the appropriate daughter board, can implement a servo drive or a CCU board.

    Right now, in our POC board the EtherCAT period is set to 1ms, but it could be lowered in the final release.
    I am aware that the TCM plays an important role in the AM6x/AM2x world!

    In the CCU application, EtherCAT master and slave apart, we need to execute some calculations, the likes of gravity compensation and speed and position check.

    So I think that we need at least 1 core free for the checker task.

    If I understand correctly, the slave stack is the one very CPU-intensive, and this is understandable.

    Do you think that 3 R5F cores and TCMs in the AM2434 could be enough to handle the EtherCAT master (1 core) and slave (1 or 2 cores) stuff @1ms?

    Many thanks again

    Michele

  • +1 in reply to michele sponchiado
    Mastermind 7490 points

    Hi Michele,

    at 1ms it's unlikely that you'll run into problems with code executing from the 2MB MSRAM oder even from DDR memory.

    Our master for example can operate at 100us cycle time, but for that we had to put all of the critical code into TCM.

    We've also used the EtherCAT slave on the AM64x with the Beckhoff SSC stack. We've put large parts of the code into TCM for that, too, again to achieve the 100us cycle time.

    If you need 3 R5f cores you can't run both R5f subsystems in single core mode, so you could have one subsystem in single core mode with 128KB TCM and one subsystem in dual core mode with 64 KB TCM each. At 1ms cycle that shouldn't be a problem. There's also the M4 MCU that you could use.

    Regards,

    Dominic

  • 0 in reply to Dominic Rath
    Prodigy 10 points

    Hi, Dominic!

    Many thanks for your help!

    Best regards

    Michele