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connecting 320vc5505 with ADC/DAC

Jim16302
Prodigy 90 points

Hi,

    I am new to 320vc5505.

    If I use 320vc5505 (master) to  periodically (1~2MHz sampling rate) to receive/get samples from ADC/DAC, how accurate can 320vc5505 output sampling clock? I read somewhere else the sampling clock from DSP generally is not very stable, is this true?

   Can any one provide a reference design on how to connect  320vc5505 with ADC/DAC?

Thanks!

 

 

  • 0
    TI__Intellectual 2530 points

    Hi Jim,

    In case you have not seen it, we have provided a project that includes interfacing the C5505 to ADC and DAC (AIC3204 codec) at:

    http://code.google.com/p/c5505-ezdsp/

    It is the audio filter demo code near the bottom of the page.  The page also has links to locations where you can find the schematics and reference documentation for the eZdsp board that has the AIC3204 interfaced to the C5505.

    Best regards, Vishal

  • 0
    Prodigy 230 points

    Jim,

    The other option is to make the ADC the master. I am doing this with a '5509A, using an external clock and a small CPLD to generate the framing signal. That way, the sampling stability is dependent primarliy on the oscillator you choose for the clock source.

    Bill

  • 0 in reply to Bill Allen
    Prodigy 90 points

    Hi, Bill and Vishal,

          Thanks a lot for your help!  I have a couple more questions:[:)]

    1) If I connect C5505 with ADC/DAC by the serial port, its maximum rate is 25MHz, can it support 2 channel ADC/DAC (each channel requires at least 1M samples per second and each sample is 8 bits)?

    2). If I use EMIF for parallel connection with ADC/DAC,  do you know if there is any reference design I can refer to? It seems by using EMIF,  it is working on asynchronized mode.  Can it provide good periodic sampling?  Our application has very high requirement on the periodicity of the sampling.

    Thanks!

    Jim

     

  • 0 in reply to Jim16302
    TI__Guru 64500 points

    Jim said:

    2). If I use EMIF for parallel connection with ADC/DAC,  do you know if there is any reference design I can refer to? It seems by using EMIF,  it is working on asynchronized mode.  Can it provide good periodic sampling?  Our application has very high requirement on the periodicity of the sampling.

    I would not advise doing this.  Even if you only allocated one master subsystem (ie. CPU or DMA engine) to the EMIF for servicing the reading of samples, the timing is not guarenteed.  I believe you will potentially incur stalls in the bus activity do to other things going on within the bus architecture internally.  Plus you would need a triggering event for the DMA, which could be a timer of some sort, or the clock of the ADC.  But there will be delay in registering this trigger, granting access of the DMA engine to the EMIF, etc.

    Many have tried this type of mechanism and the interface is just not equipped to handle this type of situation.  I realize it is appealing from the standpoint of a parallel interface, but there are limitations.  If you had a buffer externally, like a dual port RAM to use as a FIFO, this could be done, but that is an expensive alternative.

  • 0 in reply to Jim16302
    Prodigy 230 points

    Hi Jim,

    You'll have to work it out based on the number of clock cycles required per sample and this will depend on the ADC you pick. In my case, each sample requires 18 clock cycles, and my required sample rate is 1.2MSPS, so the clock is 21.6MHz. The CPLD divides the clock by 18 to provide the frame synch.

    In your case, you might have to use two seperate ADC's on two different McBSP channels. If you need synchronous samples, you can clock both channels from the same clock and frame sync. Of course, all of this will drive, or will be driven by, the particular ADC you choose.

    Bill

  • 0 in reply to Bill Allen
    Prodigy 90 points

    That is very clear and helpful, thanks!  This leads the last questions: how many device can one clock drive? (Is there any current limitation?)  We have up to 4 DAC/ADC.

  • 0 in reply to Jim16302
    Genius 4630 points

    If you only have 3 McBSP ports, then it doesn't do you any good to drive all 4 converters from the same clock - you still need an independent means of getting the data back from each converter.  Assuming you have more than 3 ADC chips, you can't get the samples from the 4th chip because there's no 4th McBSP.  Your only choice would be to stagger the data, but this could cause problems because some ADC chips use the data clock to set the sample clock.

    It might help to know your part number for the CODEC, to inform as to whether the chips have configurable clocking.  If you need all conversions to happen simultaneously, then your options are more limited than if they can be staggered.