The ibis model for the C6457 DSP (tms320c6457c.ibs) defines some models based on termination, 30/45/50/55 ohm, yet there is no mention of this in the DDR2 users guide (SPRUGK5C).
The only selection seems to be in the DDR2 Memory Controller Control Register (DMCCTL):
bits 5-4 DDRPVTCNTL bits.
0b00 No termination.
0b01 Half termination (recommended value).
0b1x Full termination.
(as well as slew rate through the external pin, DDRSLRATE)
From IBIS model (tms320c6457c.ibs) :
| -BSHTLTCSCDVGPBFZ
| the following portions of the model have been updated
| Driver:
| a) Impedance - 45/50/55 ohms impedance
| b) Slew Rate Operation - Fast and slow modes of operation
| c) Voltage Levels - 1.5/1.8V
| d) Voltage Nom variation - 10%/5%
| Reciever -
| a) Termination Modes - Half/Full Termination as well as no termination modes
| b) Termination Impedance - 45/50/55 ohms impedance
| c) Voltage Levels - 1.5/1.8V
| d) Voltage Nom variation - 10%/5%
The user guide also mentions that there is no ODT on the C6457 (from page 10 of the users guide) "On-die termination signal(s) to external DDR2 SDRAM. Note: There are no on-die termination resistors implemented on the die of the C6457 DSPs." So why are there models in the ibis for ODT?
Also, for no termination models, why are there different impedances (30/45/50/55)? Receiver Impedance? Driver impedance? How are they selected/changed in the DSP?
45OHM_5PER_NOTERM_1P8 RX MODE,1.8V +/- 5PERCENT,WITHOUT TERMINATION
|45OHM_5PER_NOTERM_1P8;
50OHM_5PER_NOTERM_1P8 RX MODE,1.8V +/- 5PERCENT,WITHOUT TERMINATION
|50OHM_5PER_NOTERM_1P8;
55OHM_5PER_NOTERM_1P8 RX MODE,1.8V +/- 5PERCENT,WITHOUT TERMINATION
|55OHM_5PER_NOTERM_1P8;
30OHM_5PER_NOTERM_1P8 RX MODE,1.8V +/- 5PERCENT,WITHOUT TERMINATION
|30OHM_5PER_NOTERM_1P8;
I am trying to do some timing verification in HyperLynx and I need to know what are valid models to use for the DSP. Thanks.