TDA4VM: How to porting new OSPI Flash device in RTOS SDK

Hi Sancho,

Sancho Huang said:

Is there any guide line for porting this device in RTOS SDK? 

I don't think there is any document available for this. 

Can you please share what issues you are facing with the boot? Can you share the logs?

Regards,
Parth

Hi, Parth

In my custom board, boot from ospi flash fail, mcu uart log indicate that Board_flashOpen failed!:

BR.

Sancho

Hi, Prth

One more question: Does the OSPI Flash device MT35XL01GABA1G12 support boot from OSPI Flash mode in RTOS SDK?

BR.

Sancho

Hi Sancho,

You'll need to change the device id and manufacture id in <pdkInstallPath>\packages\ti\board\src\flash\nor\device\m35xu512.h as well. Can you make these changes as well and try?

Regards,
Parth

Hi, Parth

I try your suggestion to change the device and manufacture id in m35xu512.h file, it also boot fail and indicate that Board_flashOpen failed!

The diff file is:

diff --git a/packages/ti/board/src/flash/include/board_flash.h b/packages/ti/board/src/flash/include/board_flash.h
index 930092a..9ddce7f 100644
--- a/packages/ti/board/src/flash/include/board_flash.h
+++ b/packages/ti/board/src/flash/include/board_flash.h
@@ -109,10 +109,10 @@ typedef int32_t Board_flash_STATUS;       /** Board Flash API return type */
 #define BOARD_FLASH_ID_MT29W160EB          (0x2249U) /**< Micron 2MB NOR flash */
 #define BOARD_FLASH_ID_MT29F4G08ABAEAWP    (0xDC90U) /**< Micron 512MB NAND flash */
 #if defined(SIM_BUILD)
-#define BOARD_FLASH_ID_MT35XU512ABA1G12    (0x5B1AU) /**< J7 VLAB SIM flash ID */
+#define BOARD_FLASH_ID_MT35XU512ABA1G12    (0x5B1BU) /**< J7 VLAB SIM flash ID */
 #define BOARD_FLASH_ID_MT35XU256ABA1G12    (0x5B1AU) /**< AM64x VLAB SIM flash ID */
 #else
-#define BOARD_FLASH_ID_MT35XU512ABA1G12    (0x5B1AU) /**< Micro 512Mb NOR flash device Id  */
+#define BOARD_FLASH_ID_MT35XU512ABA1G12    (0x5B1BU) /**< Micro 512Mb NOR flash device Id  */
 #define BOARD_FLASH_ID_MT35XU256ABA1G12    (0x5B19U) /**< Micro 256Mb NOR flash device Id  */
 #endif
 #define BOARD_FLASH_ID_MT25QU512ABB        (0xBB20) /**< 64MB NOR Flash */
diff --git a/packages/ti/board/src/flash/nor/device/m35xu512.h b/packages/ti/board/src/flash/nor/device/m35xu512.h
index d3eb619..c59eea2 100644
--- a/packages/ti/board/src/flash/nor/device/m35xu512.h
+++ b/packages/ti/board/src/flash/nor/device/m35xu512.h
@@ -106,7 +106,7 @@
 /* \brief Read ID command definitions */
 #define NOR_RDID_NUM_BYTES           (0x3U)
 #define NOR_MANF_ID                  (0x2CU)    /* Manufacturer ID */
-#define NOR_DEVICE_ID                (0x5B1A)   /* Device ID */
+#define NOR_DEVICE_ID                (0x5B1B)   /* Device ID */
 
 /** Status Register, Write-in-Progress bit */
 #define NOR_SR_WIP                   (1U << 0U)
diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c
index dc1fc6d..960e250 100755
--- a/packages/ti/boot/sbl/board/k3/sbl_main.c
+++ b/packages/ti/boot/sbl/board/k3/sbl_main.c
@@ -370,12 +370,13 @@ int main()
     SBL_ADD_PROFILE_POINT;
 
     SBL_log(SBL_LOG_MIN, "%s (%s - %s)\n", SBL_VERSION_STR, __DATE__, __TIME__);
-
+	SBL_log(SBL_LOG_MIN, "[xxx] modify the ospi flash device id\n");
     SBL_ADD_PROFILE_POINT;
 
     /* Initialize the ATCM */
     atcm_size = sblAtcmSize();
     memset((void *)SBL_MCU_ATCM_BASE, 0xFF, atcm_size);
+	SBL_log(SBL_LOG_MIN, "Initialize the ATCM\n");
 
     /* Relocate CSL Vectors to ATCM*/
     memcpy((void *)SBL_MCU_ATCM_BASE, (void *)_resetvectors, 0x100);
@@ -384,11 +385,14 @@ int main()
 
     /* Setup RAT */
     SBL_RAT_Config(sblRatCfgList);
+	SBL_log(SBL_LOG_MIN, "Setup RAT\n");
 
     SBL_ADD_PROFILE_POINT;
 
     /* Load SYSFW. */
+	SBL_log(SBL_LOG_MIN, "start to Load SYSFW\n");
     SBL_SciClientInit();
+	SBL_log(SBL_LOG_MIN, "end Load SYSFW\n");
 
     SBL_ADD_PROFILE_POINT;
 
diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk
index 4036990..4c0beba 100755
--- a/packages/ti/boot/sbl/sbl_component.mk
+++ b/packages/ti/boot/sbl/sbl_component.mk
@@ -1067,9 +1067,9 @@ export sbl_boot_xip_entry_SBL_APPIMAGEGEN
 # no logs = 0, only errors =1, normal logs = 2, all logs = 3
 
 ifeq ($(SOC), tpr12)
-SBL_CFLAGS += -DSBL_LOG_LEVEL=0
+SBL_CFLAGS += -DSBL_LOG_LEVEL=3
 else
-SBL_CFLAGS += -DSBL_LOG_LEVEL=2
+SBL_CFLAGS += -DSBL_LOG_LEVEL=3
 endif
 
 SBL_CFLAGS += -DSBL_ENABLE_PLL
@@ -1177,15 +1177,15 @@ CUST_SBL_TEST_BOARDS = am65xx_evm j721e_evm j7200_evm am64x_evm
 #CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=1 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
 ifeq ($(SOC),$(filter $(SOC), j7200 am64x))
 # NOTE: If changing to SBL_USE_DMA=1, below, then also change 'sbl_lib_cust' & 'sbl_cust_img' MAKEFILE lines further below to use 'SBL_USE_DMA=yes'
-CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
+CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
 else
   ifeq ($(findstring j7,$(SOC)),j7)
 # NOTE: If changing to SBL_USE_DMA=1, below, then also change 'sbl_lib_cust' & 'sbl_cust_img' MAKEFILE lines further below to use 'SBL_USE_DMA=yes'
-CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
+CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0xB8000000 -DSBL_SCRATCH_MEM_SIZE=0x4000000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_ENABLE_DDR -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
 # Custom ex: Early CAN response (NOTE: before using line below, comment out the line above)
 #CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_ENABLE_DEV_GRP_MCU -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_PINMUX_ENABLE -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
   else
-CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x70100000 -DSBL_SCRATCH_MEM_SIZE=0xF0000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
+CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0x70100000 -DSBL_SCRATCH_MEM_SIZE=0xF0000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
   endif
 endif
 

MT35XL01GABA1G12 datasheet show the manufacture id is 0x2C, and the device id is 0x5B1B.

the MCU uart log output is:

BR.

Sancho

Hi Sancho,

Can you please confirm the OSPI Flash part number you are using? With the mail communication that is going on, I got the part number as MT35XU01GBBA1G12-0AUT and the part number mentioned in this thread is MT35XL01GABA1G12. So, can you please confirm the what is the part number used here. 

Also, please check what is the status returned by Nor_ospiReadId in <pdkInstallPath>\packages\ti\board\src\flash\nor\ospi\nor_ospi.c and confirm that the device ID and manufacture id returned by the device matches the IDs you are configuring.

Regards,
Parth

Hi, Parth

I confirm the ospi part number is MT35XU01GBBA1G12-0AUT.

I will add some debug message in Nor_ospiReadId and feedback the test result within the day.

BR.

Sancho

Hi, Parth

In Nor_ospiReadId() function, read the manufacture id is 0x00 and device id is 0x2C5B.

Actually the manufacture id of the ospi flash is 0x2C and device id is 0x5B1B.

the MCU uart log output is:

This is my diff about nor_ospi.c file

diff --git a/packages/ti/board/src/flash/nor/ospi/nor_ospi.c b/packages/ti/board/src/flash/nor/ospi/nor_ospi.c
index 61c6469..e15a069 100755
--- a/packages/ti/board/src/flash/nor/ospi/nor_ospi.c
+++ b/packages/ti/board/src/flash/nor/ospi/nor_ospi.c
@@ -35,6 +35,8 @@
 #include <ti/board/src/flash/nor/ospi/nor_ospi.h>
 #include <ti/drv/spi/soc/SPI_soc.h>
 #include <ti/csl/soc.h>
+#include <ti/drv/uart/UART_stdio.h>^M
+#include <ti/drv/uart/UART.h>^M
 
 #if defined (j7200_evm)
 /* SPI entry offset is at index 5 of SPI config array */
@@ -118,8 +120,11 @@ static NOR_STATUS Nor_ospiReadId(SPI_Handle handle)
     retVal = NOR_ospiCmdRead(handle, &cmd, 1, idCode, NOR_RDID_NUM_BYTES);
     if (retVal == NOR_PASS)
     {
+        UART_printf("[xxx] NOR_ospiCmdRead NOR_PASS\n");^M
         manfID = (uint32_t)idCode[0];
         devID = ((uint32_t)idCode[1] << 8) | ((uint32_t)idCode[2]);
+        UART_printf("[xxx] manfID = 0x%x, devID = 0x%x\n", manfID, devID);^M
+        UART_printf("[xxx] idCode[0] = 0x%x, [1] = 0x%x, [2] = 0x%x\n", idCode[0], idCode[1], idCode[2]);^M
         if ((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID))
         {
             Nor_ospiInfo.manufacturerId = manfID;
@@ -130,6 +135,7 @@ static NOR_STATUS Nor_ospiReadId(SPI_Handle handle)
             retVal = NOR_FAIL;
         }
     }
+    UART_printf("[xxx] NOR_ospiCmdRead NOR_FAIL\n");^M
 
     return (retVal);
 }
@@ -259,13 +265,16 @@ static NOR_STATUS Nor_ospiSetDummyCycle(SPI_Handle handle, uint32_t dummyCycle)
     uint8_t                cmdWren = NOR_CMD_WREN;
     uint32_t               data[3];
     uint32_t               addrBytes;
+    UART_printf("[xxx] Nor_ospiSetDummyCycle, dummyCycle = %d\n", dummyCycle);^M
 
     if (gDtrEnable == true)
     {
+        UART_printf("[xxx] Nor_ospiSetDummyCycle, dtr enable, addrBytes = 3\n");^M
         addrBytes = 3U;
     }
     else
     {
+        UART_printf("[xxx] Nor_ospiSetDummyCycle, dtr disable, addrBytes = 2\n");^M
         addrBytes = 2U;
     }

BR.

Sancho

Hi Sancho,

Can you replace the device Id and manufacture id in the code with what is read by Nor_ospiReadId and see if it works?

Regards,
Parth

Hi, Parth

1. Yes, I only know we use DDR part number is MT53D1024M32D4DS-053:B(4GB,4266MHz), I will contact our hardware team about the detail of DDR change.

I upload the DDR config file board_ddrRegInit, I hope it will be helpful to investigate the problem

board_ddrRegInit.zip

2. I try to use SBL+SD to diagnoist test DDR, but the SBL+SD boot fail, the question is TDA4VM: SBL SD Boot - tifs File open fails

3. I will add more debug message when DDR is initializing and feedback within a day.

BR.

Sancho

Hi, Parth

I try to add some debug message in board_ddr.c and lpddr4.c when initialize DDR and found it hang in LPDDR4_StartSequenceController() function.
Do you have any suggestion about this problem?

The MCU uart log output is:

This is my diff about lpddr4.c file

diff --git a/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c b/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
index 3b7f228..0924a9b 100644
--- a/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
+++ b/packages/ti/csl/src/ip/lpddr/V0/priv/lpddr4.c
@@ -47,6 +47,9 @@
 #include "lpddr4_ctl_regs_rw_masks.h"
 #endif
 
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/uart/UART.h>
+
 #ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
 #define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
 #endif
@@ -248,6 +251,7 @@ uint32_t LPDDR4_Start(const LPDDR4_PrivateData* pD)
     uint32_t result = 0U;
     uint32_t regVal = 0U;
 
+    UART_printf("[xxx] in LPDDR4_Start start\n");
     result = LPDDR4_StartSF(pD);
     if (result == (uint32_t)CDN_EOK) {
         LPDDR4_CtlRegs* ctlRegBase = (LPDDR4_CtlRegs*)pD->ctlBase;
@@ -258,8 +262,11 @@ uint32_t LPDDR4_Start(const LPDDR4_PrivateData* pD)
         CPS_REG_WRITE((&(ctlRegBase->LPDDR4__PI_INIT_LVL_EN__REG)), regVal);
 
         /* Start PI init sequence. */
+        UART_printf("[xxx] LPDDR4_StartSequenceController start\n");
         result = LPDDR4_StartSequenceController(pD);
+        UART_printf("[xxx] LPDDR4_StartSequenceController end\n");
     }
+    UART_printf("[xxx] in LPDDR4_Start end\n");
     return result;
 }

BR.

Sancho

Hi Sancho,

Looks like there is something wrong with the DDR configurations. Re-assigning this thread to a DDR expert. He'll respond here soon.

Regards,
Parth

Hi Parth,

Thank you for you support, OSPI Flash Board_flashOpen failed have been solved.
I will ask a new question about "Initlialzing DDR ..." and close this quesion.

BR.
Sancho