AM6442: Is there any possibility to occur unintended hazard at the IO pins ?

Hello Hideaki,

Thank you for he query.

Most AM64x IOs are not fail-safe, so precautions must be taken to ensure no external device sources a potential to these IOs before their respective power rails are valid.  However, it sounds like customer design is applying power to AM64x before the attached devices.  If so, customer would need to confirm our device doesn’t source any potential to attached devices unless they have fail-safe IOs. 

Note: The IOs of most CMOS devices are not fail-safe, so you should always assume they are not unless stated otherwise.

 Most AM64x IOs are configured to have their input buffers disabled, output drivers disabled, and internal pull-up/pull-down resistors disabled. This makes the system design easier to implement since we do not source any potential until software configures the IOs. 

There are a few exceptions and the customer can confirm the default states of each IO connected to their external devices by reviewing information provided in the Ball State During Reset and Ball State After Reset columns of the Pin Attributes table, where the following descriptions apply.  They may also need to consider the impact of AM64x IOs the ROM code attempts to use once reset is released.  The TRM has a section that defines which IOs are used by each boot mode selected.

Please refer to the datasheet and TRM for more details on the IOs.

Regards,

Sreenivas

Hi Sreenivas,

Thank you so much for your answer. The customer would like to add one more question about the behavior of IO during power-on.

Regarding the IOs of AM64xx, they’re concerned about whether the IO outputs any electrical something like dust signal while the power of 1.8V for IOs are turned on and before the voltage rises to the minimum operating voltage.

They understand that if the IOs go above the minimum operating voltage, the IOs will be High-z because the input buffer, output buffer, and internal Pull Up / Pull Down resistance are disabled. Are they correct ?

They worry about a bad influence to the external devices which is not yet power on by output from IOs of AM64x.

AM64xx raises the core voltage after power-up of IO voltage, so they are a little worried.

Thanks and regards,

Hideaki

Hello Hideaki, 

Thank you for checking.

Can you please confirm if customer has read the below.

Most AM64x IOs are configured to have their input buffers disabled, output drivers disabled, and internal pull-up/pull-down resistors disabled. This makes the system design easier to implement since we do not source any potential until software configures the IOs. 

There are a few exceptions and the customer can confirm the default states of each IO connected to their external devices by reviewing information provided in the Ball State During Reset and Ball State After Reset columns of the Pin Attributes table, where the following descriptions apply.  They may also need to consider the impact of AM64x IOs the ROM code attempts to use once reset is released.  The TRM has a section that defines which IOs are used by each boot mode selected.

Also, would it be possible for customer to elaborate the concern and also provide some additional details on the application use case.

Regards,

Sreenivasa

Hi Sreenivasa,

Yes, they read your answers.

>    They recognized that if the IOs go above the minimum operating voltage, the IOs will be High-z because the input buffer, output buffer, and internal Pull Up / Pull Down resistance are disabled. Are they correct ?

The above thier recognition is correct ?

Their design is following the Application note like below block diagram, but the peripheral devices are 1.8V powered by DCDC3 drawn as red circles in the following diagram. Therefore, LDO 1.8V IO (VDDSHVy) circled as blue is powered up earlier than 1.8V power rail from DCDC3 circled in red.

They're concerned if AM64x IO sources a potential to the external devices which not yet powered by DCDC3.

They think that there is no problem in this system because the architecture is the almost same as that in Application note. Are they correct ?

Thnaks and regards,
Hideaki