TDA4VM: J784S4X SerDes1 Clock Usage Confirmation

I am assuming this question is for the J784S4X (AHP) device?  The SERDES can only source 1 internal clock.  If a 2nd clock source is needed, it needs to be external.  In your scenario - the PCIe should used externally provided clock (via the SERDES1_REFCLK pins) and the SGMII interfaces can use internally generated clock.  In this example, the PCIe_REFCLKx_OUT pins would be left open.

Thanks for replying our question. But, can you please provide block diagram for your explanation to understand us better.

SGMII1, SGMII2 can use internally generated clock

PCIe0 can use externally generated clock input on pins SERDES_REFCLK

PCIe_REFCLK_OUT pins will be left unconnected

Thanks for clarification.

But this is conflicting to answer of my other question " TDA4VM: J784S4X- SERDES0 and PCIE REFCLK usage". 

I have moved this question there for better clarity.