AM6442: RTU and ADC interface

Hello Kelvin, 

Thank you for the query.

How many ADCs can be connected to an ICSSG slice (e.g. 1 PRU, 1 RTU)?

Can you please share any additional information you may have on the ADC that you are looking to interface and the use case.

Regards,

Sreenivasa

It's a preleased part but similar to ADS9224R.  The configuration is 10 Mbps, 16 bit on 2 wire LVDS DDR.  DS90LV012 will be used to convert LVDS to CMOS.

But this just a general question.  Can the RTU support ADC interface without access to the I/O?

Hello Kelvin, 

Thank you for the query.

But this just a general question.  Can the RTU support ADC interface without access to the I/O?

Did you mean ADC data processing or ADC interface ?

Regards,

Sreenivasa

ADC Interface

Hello Kelvin, 

Thank you for the reply.

The main difference between the PRU and RTU cores is that the RTUs don't have any access to I/Os. The RTUs are strictly available for data processing, while the PRUs can be used for I/O control and/or data processing.

Do you have an interface bock diagram ?

I can check internally if i have some additional information.

https://training.ti.com/zh-tw/pruicssg-overview

Regards,

Sreenivasa

Hello Kevin, 

Please refer below 

PRU cores have direct signal connections to the PRU GPI/GPO pins from their R30/R31 registers. RTU cores do NOT have a signal path to the PRU GPI/GPO pins. You can use the RTU cores to control the on-chip ADC for processors that have an on-chip ADC, or you can control GPIO pins, the SPI peripherals, etc. But the RTU signals have to go through the system bus to reach those pins instead of having a direct connection, so the read/write latencies will be much longer.

 In general, if the customer is trying to use the PRU_ICSSG cores to bitbang a signal (instead of controlling a peripheral, where the peripheral implements the signal), I would suggest only using cores that have a direct signal path to the PRU GPI/GPO pins.

Regards,

Sreenivasa