Loading program to SRAM

Are you using DSP/BIOS?

Jayaprakash,

The linker (part of Code Generation Tools) performs the allocation of your program to the physical memory space of your target board.  In this case the C5505 EVM.  The linker uses a command file (.cmd extension) that defines both the physical memory of the system and how you want your code and data allocated to that memory.  If you use DSP/BIOS, then the .cmd file configuration is done through BIOS configuration manager.  If you don't use DSP/BIOS, then you must develop the .cmd file yourself (or modify the one you have).  If you can share your .cmd file, then it will be easier to help you make the changes you want to make.

Regards.

Hi Marina,

no. We are not using DSP/BIOS.

Actaully our .out file size is very big, so we cannot use the IRAM.

In SECTION part of the command (.cmd ) file defines the some parameters like stack, dat, bss, text etc. So which all parameters we need to modify so that i can load my .out file to SRAM and execute it.

Thank you,

Jayaprakash

Can you copy your cmd file here at the forum as Tom suggested?

Basically ,you need to have a memory defined for the address range of the external memory, then you need to start pointing parts of your code data to your that section. If you put your cmd here it would be easier to guide you.

So do you have a daughtercard with SRAM hooked up?  You would also need to add some code to the OnConnect() function of your gel file to initialize the EMIF so that CCS can load the code to that memory.

Hi Tommy,

Find the command file below.. Sorry for the late reply as i had network problem.

-c
-stack 0x200                   /* PRIMARY STACK SIZE               */
-sysstack 0x200                /* SECONDARY STACK SIZE             */
-heap  0x1000                   /* HEAP AREA SIZE   */ 

_RTDX_interrupt_mask = ~0x06000010;

-e reset_isr

MEMORY
{
    MMR     (RW)  : origin = 0000000h length = 0000c0h /* MMRs */
    VEC     (RX)  : origin = 00000C0h length = 000300h /* on-chip ROM vectors */
    DARAM_0 (RW)  : origin = 0000400h length = 001A00h /* on-chip DARAM 0 */
    DARAM_1 (RW)  : origin = 0002000h length = 002000h /* on-chip DARAM 1 */
    DARAM_2 (RW)  : origin = 0004000h length = 002000h /* on-chip DARAM 2 */
    DARAM_3 (RW)  : origin = 0006000h length = 002000h /* on-chip DARAM 3 */

    DARAM_4 (RW)  : origin = 0008000h length = 002000h /* on-chip DARAM 4 */
    DARAM_5 (RW)  : origin = 000A000h length = 002000h /* on-chip DARAM 5 */
    DARAM_6 (RW)  : origin = 000C000h length = 002000h /* on-chip DARAM 6 */
    DARAM_7 (RW)  : origin = 000e000h length = 002000h /* on-chip DARAM 7 */
    
      SARAM_0 (RW)  : origin = 0010000h length = 0010000h   /* on-chip SARAM 0 */
    SARAM_8 (RW)  : origin = 0020000h length = 002000h  /* on-chip SARAM 8 */
    SARAM_9 (RW)  : origin = 0022000h length = 002000h  /* on-chip SARAM 9 */
    SARAM_10 (RW) : origin = 0024000h length = 002000h  /* on-chip SARAM 10 */
    SARAM_11 (RW) : origin = 0026000h length = 002000h  /* on-chip SARAM 11 */

    SARAM_12 (RW) : origin = 0028000h length = 002000h  /* on-chip SARAM 12 */
    SARAM_13 (RW) : origin = 002A000h length = 002000h  /* on-chip SARAM 13 */
    SARAM_14 (RW) : origin = 002C000h length = 002000h  /* on-chip SARAM 14 */
    SARAM_15 (RW) : origin = 002e000h length = 002000h  /* on-chip SARAM 15 */

    SARAM_16 (RW) : origin = 0030000h length = 002000h  /* on-chip SARAM 16 */
    SARAM_17 (RW) : origin = 0032000h length = 002000h  /* on-chip SARAM 17 */
    SARAM_18 (RW) : origin = 0034000h length = 002000h  /* on-chip SARAM 18 */
    SARAM_19 (RW) : origin = 0036000h length = 002000h  /* on-chip SARAM 19 */

    SARAM_20 (RW) : origin = 0038000h length = 002000h  /* on-chip SARAM 20 */
    SARAM_21 (RW) : origin = 003A000h length = 002000h  /* on-chip SARAM 21 */
    SARAM_22 (RW) : origin = 003C000h length = 002000h  /* on-chip SARAM 22 */
    SARAM_23 (RW) : origin = 003e000h length = 002000h  /* on-chip SARAM 23 */

    SARAM_24 (RW) : origin = 0040000h length = 002000h  /* on-chip SARAM 24 */
    SARAM_25 (RW) : origin = 0042000h length = 002000h  /* on-chip SARAM 25 */
    SARAM_26 (RW) : origin = 0044000h length = 002000h  /* on-chip SARAM 26 */
    SARAM_27 (RW) : origin = 0046000h length = 002000h  /* on-chip SARAM 27 */

    SARAM_28 (RW) : origin = 0048000h length = 002000h  /* on-chip SARAM 28 */
    SARAM_29 (RW) : origin = 004A000h length = 002000h  /* on-chip SARAM 29 */
    SARAM_30 (RW) : origin = 004C000h length = 002000h  /* on-chip SARAM 30 */
    SARAM_31 (RW) : origin = 004E000h length = 002000h  /* on-chip SARAM 31 */  

    SAROM_0 (RX)  : origin = 0ff0000h length = 008000h  /* on-chip ROM 0 */
    SAROM_1 (RX)  : origin = 0ff8000h length = 007f00h  /* on-chip ROM 1 */
   
    EMIF_CS0 (RW)  : origin = 0050000h  length = 07B0000h   /* mSDR */
 EMIF_CS2 (RW)  : origin = 0800000h  length = 0400000h   /* ASYNC1 : NAND */
 EMIF_CS3 (RW)  : origin = 0C00000h  length = 0200000h   /* ASYNC2 : NOR  */
 EMIF_CS4 (RW)  : origin = 0E00000h  length = 0100000h   /* ASYNC3 : SRAM */
 EMIF_CS5 (RW)  : origin = 0F00000h  length = 00F0000h   /* ASYNC4 : SRAM */
}

SECTIONS
{
    .intvecs     : > VEC   ALIGN = 256
    .text       : > SARAM_0  ALIGN = 4
    stack       : > SARAM_20  ALIGN = 2
    sysstack      : > SARAM_20  ALIGN = 2
 .cio        : > SARAM_20  ALIGN = 2
   
    .rtdx_text       > DARAM_0              
 .rtdx_data       > DARAM_2 fill=0xBEEF   
 .pinit           > SARAM_0 

    .data       : > DARAM_0
    .bss        : > DARAM_0, fill = 0
 .cinit   : > DARAM_1
 .const   : > DARAM_1
  sysmem  : > DARAM_1

 .buffer1    : > DARAM_2
 .buffer2    : > DARAM_2
 .buffer3    : > DARAM_3
 .buffer4    : > DARAM_3
 .buffer5    : > DARAM_4
 .buffer6    : > DARAM_5
 .buffer7    : > DARAM_6
 .buffer8    : > DARAM_7
 .buffer11   : > SARAM_20
 .buffer12   : > SARAM_23
 .buffer13   : > SARAM_24
 .buffer14   : > SARAM_25
 .buffer15   : > SARAM_26
 .buffer16   : > SARAM_27
 .buffer17   : > SARAM_28
 .buffer18   : > SARAM_29
 .buffer19   : > SARAM_10
 .buffer20   : > SARAM_11
 .buffer21   : > SARAM_12
 .buffer22   : > SARAM_13
 .buffer23   : > SARAM_14
 .buffer24   : > SARAM_15
 .buffer25   : > SARAM_16
 .buffer26   : > SARAM_17
 .buffer27   : > SARAM_18
 .buffer28   : > SARAM_19
 .buffer29   : > SARAM_20
 .buffer30   : > SARAM_21
 .buffer31   : > SARAM_22
 .buffer32   : > SARAM_23
 .buffer33   : > SARAM_24
 .buffer34   : > SARAM_25
 .buffer35   : > SARAM_26
 .buffer36   : > SARAM_27
 .buffer37   : > SARAM_28
 .buffer38   : > SARAM_29
 .buffer39   : > SARAM_30
 .buffer40   : > SARAM_31
 .emif_cs2   : > EMIF_CS2
 .emif_cs3   : > EMIF_CS3
 .emif_cs4   : > EMIF_CS4
 .emif_cs5   : > EMIF_CS5

}

Hi Marina,

Now we are planning to use DSP/BIOS. So can you let me know what changes needs to be done for executing code from SRAM.

I tried modifying memory section in tcf file, but its not working.

Hi,

Yes. we have a daughtercard.  I have changed the gel file for initializing EMIF.

Without DSP/BIOS, i am able to load .out to SRAM.

Now with DSP/BIOS we need to modify .tcf file.  Can you help me regarding this.

We can help but please be more specific with your question.  What is broken or what are you trying to do?

In DSP/BIOS, you would select the memory for the section you want in the tcf file:

HI,

   I tried loading from SRAM by using command file and also by changing .tcf file and its working fine.

   Thank you for your suggestions Marina, Tommy and Brad.

Thank you,

Jayaprakash.BS