Hello
I am trying to receive the mailbox event on the dsp core of my OMAP3530. I am using the CodeComposerStudio 4.0 as IDE. Although I have tested and configured nearly everthing possible I cannot receive the mailbox full event.
So far I have configured and tested the following things:
1. IRQ Configuration on DSP-Side
- setup the IRQ-Handler infrastructure
- enabled IRQ4 in the register IER
- enabled NMI in the register IER
- enabled GIE in the register CSR/TSR
-> when I set the IRQ4 event flag (register IFR) via the debugger, the ISR of the IRQ4 gets called as expected
2. Event Generation on the Mailbox side
- Set bit 0 of MAILBOX_IRQENABLE_1 (IRQ for new message in messagebox 0)
- Checked bit 0 of the register MAILBOX_IRQSTATUS_1
-> the bit 0 of the register MAILBOX_IRQSTATUS_1 is set, the event should be forwarded to the WUGEN
3. WUGEN configuration
- Unmasked all WUGEN-Events
- Checked masks and events -> all masks zeroed (WUGEN_MEVT0 - WUGEN_MEVT1 set to 0x00000000)
- Checked behaviour with all masked events (according to the manual the flags are sticky as long as the event is masked)
-> there are never flags set in the registers WUGEN_PENDEVTx
4. INTC configuration
- Unmasked event 55 (mailbox event) in EVTMASK_1 (set to 0xFF7FFFFF)
- Masked all exceptions
- Masked all Dropped Events
- Set INTMUX_1 to 0x07060537 (IRQ4 -> event 55)
- Checked event generation by setting the EVTFLAG_1 manually -> no reaction, the IRQ4-handler never gets called.
- Checked event generation by setting the EVTFLAG_1 and using combined event (INTMUX1 = 0x07060501) -> the IRQ4-handler gets called
Obviously I am missing some necessary configuration. Can you tell me what I am doing wrong? For me it looks like the WUGEN and/or the INTC is not working. Do I have to enable some additional functional clock (e.g. the IVA_INTC_FCLK mentioned in spruf98r, page 1035 -> IVA_INTC_FCLK does not occur somewhere else in the document)? Or is there another mask register? Must the ARM-Core enable something to get things to work?
Thanks
Simon